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1 copyright ? cirrus logic, inc. 2000 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com cs5521/22/23/24/28 16-bit or 24-bit, 2/4/8-channel adcs with pgia features l low input current (100 pa), chopper stabilized instrumentation amplifier l scalable input span (bipolar/unipolar) - 2.5v vref: 25 mv, 55 mv, 100 mv, 1 v, 2.5 v, 5v - external: 10 v, 100 v l wide v ref input range (+1 to +5 v) l fourth order delta-sigma a/d converter l easy to use three-wire serial interface port - programmable/auto channel sequencer with conversion data fifo - accessible calibration registers per channel - compatible with spi tm and microwire tm l system and self-calibration l eight selectable word rates - up to 617 hz (xin = 200 khz) - single conversion settling - 50/60 hz 3 hz simultaneous rejection l single +5 v power supply operation - charge pump drive for negative supply - +3 to +5 v digital supply operation l low power consumption: 5.5 mw general description the cs5521/22/23/24/28 are highly integrated ds ana- log-to-digital converters (adcs) which use charge- balance techniques to achieve 16-bit (cs5521/23) and 24-bit (cs5522/24/28) performance. the adcs come as either two-channel (cs5521/22), four-channel (cs5523/24), or eight-channel (cs5528) devices, and include a low input current, chopper-stabilized instru- mentation amplifier. to permit selectable input spans of 25 mv, 55 mv, 100 mv, 1 v, 2.5 v, and 5 v, the adcs include a pga (programmable gain amplifier). to ac- commodate ground-based thermocouple applications, the devices include a charge pump drive which pro- vides a negative bias voltage to the on-chip amplifiers. these devices also include a fourth order ds modulator followed by a digital filter which provides eight selectable output word rates . the digital filters are designed to settle to full accuracy within one conversion cycle and when operated at word rates below 30 hz, they reject both 50 and 60 hz interference. these single supply products are ideal solutions for measuring isolated and non-isolated, low-level signals in process control applications. ordering information see page 51. programmable gain va+ agnd vref+ vref- vd+ dgnd xin xout sdo sdi nbv latch differential digital filter calibration register control register output register 4th order ds modulator calibration memory calibration m c clock gen. sclk cs mux ain2+ + x20 x1 x1 x1 cs5524 shown ain2- ain1+ ain1- ain4+ ain4- ain3+ ain3- a0 a1 cpd data fifo may 00 ds317f2
cs5521/22/23/24/28 2 ds317f2 table of contents 1. characteristics and specifications ........................................................................ 5 analog characteristics ................................................................................................ 5 typical rms noise, cs5521/23.......................................................................................... 7 typical noise free resolution (bits), cs5521/23 .................................................... 7 typical rms noise, cs5522/24/28..................................................................................... 8 typical noise free resolution (bits), cs5522/24/28 ............................................... 8 5 v digital characteristics........................................................................................... 9 3 v digital characteristics........................................................................................... 9 dynamic characteristics ............................................................................................ 10 recommended operating conditions ..................................................................... 10 absolute maximum ratings ......................................................................................... 10 switching characteristics ........................................................................................ 11 2. general description ..................................................................................................... 13 2.1 analog input .............................................................................................................. ....... 13 2.1.1 instrumentation amplifier ......................................................................................... 14 2.1.2 coarse/fine charge buffers ............................................................................... 14 2.1.3 analog input span considerations .......................................................................... 15 2.1.4 measuring voltages higher than 5 v .................................................................. 15 2.1.5 voltage reference .............................................................................................. 16 2.2 overview of adc register structure and operating modes ............................................ 16 2.2.1 system initialization ............................................................................................ 18 2.2.2 serial port initialization sequence ...................................................................... 18 2.2.3 command register quick reference ............................................................... 19 2.2.4 command register descriptions ........................................................................ 20 2.2.5 serial port interface ............................................................................................ 25 2.2.6 reading/writing the offset, gain, and configuration registers .......................... 26 2.2.7 reading/writing the channel-setup registers ................................................... 26 2.2.7.1 latch outputs ...................................................................................... 28 2.2.7.2 channel select bits ............................................................................. 28 2.2.7.3 output word rate selection ............................................................... 28 2.2.7.4 gain bits .............................................................................................. 28 2.2.7.5 unipolar/bipolar bit ............................................................................. 28 2.2.8 configuration register ........................................................................................ 28 2.2.8.1 chop frequency select ....................................................................... 28 2.2.8.2 conversion/calibration control bits .................................................... 28 2.2.8.3 power consumption control bits ........................................................ 28 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ spi? is a trademark of motorola inc., microwire? is a trademark of national semiconductor corp. preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product information describes products which are in development and subject to development changes. cirrus logic, inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. however, the information is subject to chan ge without notice and is provided as is without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. f or the use of this information, nor for infringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, trademarks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval sys- tem, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise). furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names o f products of cirrus logic, inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respec tive owners which may be registered in some jurisdictions. a list of cirrus logic, inc. trademarks and service marks can be found at http:/ /www.cirrus.com.
cs5521/22/23/24/28 ds317f2 3 2.2.8.4 charge pump disable ......................................................................... 29 2.2.8.5 reset system control bits .................................................................. 29 2.2.8.6 data conversion error flags .............................................................. 29 2.3 calibration ............................................................................................................... ........ 31 2.3.1 self calibration .................................................................................................... 31 2.3.2 system calibration .............................................................................................. 32 2.3.3 calibration tips ................................................................................................... 34 2.3.4 limitations in calibration range ......................................................................... 34 2.4 performing conversions and reading the data conversion fifo .................................. 34 2.4.1 conversion protocol ............................................................................................ 35 2.4.1.1 single, one-setup conversion ........................................................... 35 2.4.1.2 repeated one-setup conversions without wait ................................ 35 2.4.1.3 repeated one-setup conversions with wait ..................................... 36 2.4.1.4 single, multiple-setup conversions .................................................... 36 2.4.1.5 repeated multiple-setup conversions without wait ........................... 37 2.4.1.6 repeated multiple-setup conversions with wait ................................ 37 2.4.2 calibration protocol ............................................................................................. 38 2.4.3 example of using the csrs to perform conversions and calibrations .............. 38 2.5 conversion output coding .............................................................................................. 40 2.5.1 conversion data fifo descriptions ................................................................... 41 2.6 digital filter ........................................................................................................... .......... 42 2.7 clock generator ........................................................................................................... ... 42 2.8 power supply arrangements ........................................................................................... 43 2.8.1 charge pump drive circuits ............................................................................... 45 2.9 digital gain scaling ..................................................................................................... ... 45 2.10 getting started .......................................................................................................... .... 46 2.11 pcb layout ............................................................................................................... .... 47 3. pin descriptions .......................................................................................................... .... 48 3.1 clock generator ........................................................................................................... ... 49 3.2 control pins and serial data i/o ..................................................................................... 49 3.3 measurement and reference inputs ............................................................................... 49 3.4 power supply connections ............................................................................................. 50 4. specification definitions ............................................................................................. 51 5. ordering guide ............................................................................................................ .... 51 6. package dimension drawings ................................................................................... 52
cs5521/22/23/24/28 4 ds317f2 list of figures figure 1. continuous running sclk timing (not to scale) ......................................................... 12 figure 2. sdi write timing (not to scale) ..................................................................................... 1 2 figure 3. sdo read timing (not to scale) ................................................................................... 12 figure 4. multiplexer configurations........................................................................................... ... 13 figure 5. input models for ain+ and ain- pins, (100 mv input ranges...................................... 14 figure 6. input models for ain+ and ain- pins, >100 mv input ranges ........................................ 14 figure 7. input ranges greater than 5 v ...................................................................................... 16 figure 8. input model for vref+ and vref- pins........................................................................ 16 figure 9. cs5523/24 register diagram ........................................................................................ 17 figure 10. command and data word timing................................................................................ 25 figure 11. self calibration of offset (low ranges)....................................................................... 32 figure 12. self calibration of offset (high ranges) ...................................................................... 32 figure 13. self calibration of gain (all ranges) ........................................................................... 32 figure 14. system calibration of offset (low ranges) ................................................................. 32 figure 15. system calibration of offset (high ranges) ................................................................ 33 figure 16. system calibration of gain (low ranges) ................................................................... 33 figure 17. system calibration of gain (high ranges) .................................................................. 33 figure 18. filter response (normalized to output word rate = 1) .............................................. 42 figure 19. typical linearity error for cs5521/23 .......................................................................... 42 figure 20. typical linearity error for cs5522/24/28 ..................................................................... 42 figure 21. cs5522 configured to use on-chip charge pump to supply nbv ................................ 43 figure 22. cs5522 configured for ground-referenced unipolar signals....................................... 44 figure 23. cs5522 configured for single supply bridge measurement ....................................... 44 figure 24. charge pump drive circuit for vd+ = 3 v.................................................................... 45 figure 25. alternate nbv circuits .............................................................................................. ... 45 list of tables table 1. relationship between full scale input, gain factors, and internal analog signal limitations ............................................................................................................. 15 table 2. command register quick reference.............................................................................. 19 table 3. channel-setup registers ............................................................................................... .27 table 4. configuration register................................................................................................ ..... 30 table 5. offset and gain registers ............................................................................................. .. 31 table 6. output coding for 16-bit cs5521/23 and 24-bit cs5522/24/28 ...................................... 40
cs5521/22/23/24/28 ds317f2 5 1. characteristics and specifications analog characteristics (t a = 25 c; va+, vd+ = 5 v 5%; vref+ = 2.5 v, vref- = agnd, nbv = -2.1 v, xin = 32.768 khz, cfs1-cfs0 = 00, owr (output word rate) = 15 hz, bipolar mode, input range = 100 mv; see notes 1 and 2.) notes: 1. applies after system calibration at any temperature within -40 c ~ +85 c. 2. specifications guaranteed by design, characterization, and/or test. 3. specification applies to the device only and does not include any effects by external parasitic thermocouples. lsb n : n is 16 for the cs5521/23 and n is 24 for the cs5522/24/28 4. drift over specified temperature range after calibration at power-up at 25 c. 5. measured with charge pump drive off. 6. all outputs unloaded. all input cmos levels and the cs5521/23 do not have a low power mode. parameter cs5521/23 cs5522/24/28 unit min typ max min typ max accuracy resolution --16--24bits linearity error - 0.0015 0.003 - 0.0007 0.0015 %fs bipolar offset (note 3) - 12 - 16 32 lsb n unipolar offset (note 3) - 2 4- 32 64 lsb n offset drift (notes 3 and 4) - 20 - - 20 - nv/c bipolar gain error - 8 31 - 8 31 ppm unipolar gain error - 16 62 - 16 62 ppm gain drift (note 4) - 1 3 - 1 3 ppm/c power supplies power supply currents (normal mode) i a+ (note 5)i d+ i nbv - - - 0.9 90 260 1.2 135 375 - - - 1.5 90 525 1.9 135 700 ma a a power consumption (note 6) normal mode low power mode standby sleep - n/a - - 5.5 n/a 1.2 500 7.5 n/a - - - - - - 9 5.5 1.2 500 12 7.5 - - mw mw mw w power supply rejection positive supplies dc nbv - - 120 110 - - - - 120 110 - - db db
cs5521/22/23/24/28 6 ds317f2 analog characteristics (continued) notes: 7. for the cs5528, the 25 mv, 55 mv and 100 mv ranges cannot be used unless nbv is powered at -1.8 to -2.5 v 8. see the section of the data sheet which discusses input models. chop clock is 256 hz (xin/128) for pgia (programmable gain instrumentation amplifier). xin = 32.768 khz. 9. the maximum full scale signal can be limited by saturation of circuitry within the internal signal path. parameter min typ max unit analog input common mode + signal on ain+ or ain- bipolar/unipolar mode nbv = -1.8 to -2.5 v range = 25 mv, 55 mv, or 100 mv range = 1 v, 2.5 v, or 5 v nbv = agnd range = 25 mv, 55 mv, or 100 mv (note 7) range = 1 v, 2.5 v, or 5 v -0.150 nbv 1.85 0.0 - - - - 0.950 va+ 2.65 va+ v v v v cvf current on ain+ or ain- (note 8) range = 25 mv, 55 mv, or 100 mv range = 1 v, 2.5 v, or 5 v - - 100 10 300 - pa na input current drift (note 8) range = 25 mv, 55 mv, or 100 mv - 1 - pa/c input leakage for multiplexer when off - 10 - pa common mode rejection dc 50, 60 hz - - 120 120 - - db db input capacitance - 10 - pf voltage reference input range (vref+) - (vref-) 1 2.5 va+ v vref+ (vref-)+1 -va+v vref- nbv - (vref+)-1 v cvf current (note 8) - 5.0 - na common mode rejection dc 50, 60 hz - - 110 130 - - db db input capacitance - 16 - pf system calibration specifications full scale calibration range (vref = 2.5v) bipolar/unipolar mode 25 mv 55 mv 100 mv 1 v 2.5 v 5 v 10 25 40 0.40 1.0 2.0 - - - - - - 32.5 71.5 105 1.30 3.25 va+ mv mv mv v v v offset calibration range bipolar/unipolar mode 25 mv 55 mv 100 mv (note 9) 1 v 2.5 v 5 v - - - - - - - - - - - - 12.5 27.5 50 0.5 1.25 2.50 mv mv mv v v v
cs5521/22/23/24/28 ds317f2 7 typical rms noise, cs5521/23 (notes 10 and 11) notes: 10. wideband noise aliased into the baseband. referred to the input. typical values shown for 25 c. 11. to estimate peak-to-peak noise, multiply rms noise by 6.6 for all ranges and output rates. 12. for input ranges <100 mv and output rates 3 60 hz, 16.384 khz chopping frequency is used. typical noise free resolution (bits), cs5521/23 (note 13) notes: 13. for bipolar mode, the number of bits of noise free resolution is log((2xinput range)/(6.6xrms noise))/log(2) rounded to the nearest bit. for unipolar mode, the number of bits of noise free resolution is log((input range)/(6.6xrms noise))/log(2) rounded to the nearest bit. also, the cs5521/23s output conversions are 16 bits. noise free resolution numbers are based upon vref = 2.5 v and xin = 32.768 khz. the values will be affected directly by changes in vref, but the effects due to changes in the xin frequency will be minor. output rate (hz) -3 db filter frequency input range, (bipolar/unipolar mode) 25 mv 55 mv 100 mv 1 v 2.5 v 5 v 1.88 1.64 90 nv 148 nv 220 nv 1.8 v 3.9 v 7.8 v 3.76 3.27 122 nv 182 nv 310 nv 2.6 v 5.7 v 11.3 v 7.51 6.55 180 nv 267 nv 435 nv 3.7 v 8.5 v 18.1 v 15.0 12.7 280 nv 440 nv 810 nv 5.7 v 14 v 28 v 30.0 25.4 580 nv 1.1 v 2.1 v 18.2 v 48 v 96 v 61.6 (note 12) 50.4 2.6 v 4.9 v 8.5 v 92 v 238 v 390 v 84.5 (note 12) 70.7 11 v 27 v 43 v 458 v 1.1 mv 2.4 mv 101.1 (note 12) 84.6 41 v 72 v 130 v 1.2 mv 3.4 mv 6.7 mv output rate (hz) -3 db filter frequency input range, (bipolar mode) 25 mv 55 mv 100 mv 1 v 2.5 v 5 v 1.88 1.64 16 16 16 16 16 16 3.76 3.27 16 16 16 16 16 16 7.51 6.55 15 16 16 16 16 16 15.0 12.7 15 15 15 16 16 16 30.0 25.4 14 14 14 14 14 14 61.6 (note 12) 50.4 12 12 12 12 12 12 84.5 (note 12) 70.7 9 9 9 9 9 9 101.1 (note 12) 84.6 8 8 8 8 8 8
cs5521/22/23/24/28 8 ds317f2 typical rms noise, cs5522/24/28 (notes 14 and 15) notes: 14. wideband noise aliased into the baseband. referred to the input. typical values shown for 25 c. 15. to estimate peak-to-peak noise, multiply rms noise by 6.6 for all ranges and output rates. 16. for input ranges <100 mv and output rates 3 60 hz, 16.384 khz chopping frequency is used. typical noise free resolution (bits), cs5522/24/28 (note 17) notes: 17. for bipolar mode, the number of bits of noise free resolution is log((2xinput range)/(6.6xrms noise))/log(2) rounded to the nearest bit. for unipolar mode, the number of bits of noise free resolution is log((input range)/(6.6xrms noise))/log(2) rounded to the nearest bit. also, the cs5522/24/28s output conversions are 24 bits. noise free resolution numbers are based upon vref = 2.5 v and xin = 32.768 khz. the values will be affected directly by changes in vref, but the effects due to changes in the xin frequency will be minor. output rate (hz) -3 db filter frequency input range, (bipolar/unipolar mode) 25 mv 55 mv 100 mv 1 v 2.5 v 5 v 1.88 1.64 90 nv 95 nv 140 nv 1.5 v 3 v 6 v 3.76 3.27 110 nv 130 nv 190 nv 2 v 4 v 8 v 7.51 6.55 170 nv 200 nv 275 nv 2.5 v 6 v 11.5 v 15.0 12.7 250 nv 330 nv 580 nv 4.5 v 10 v 20 v 30.0 25.4 500 nv 1 v 1.5 v 16 v 45 v 85 v 61.6 (note 16) 50.4 2 v 4 v 8 v 72 v 195 v 350 v 84.5 (note 16) 70.7 10 v 20 v 35 v 340 v 900 v 2 mv 101.1 (note 16) 84.6 30 v 60 v 105 v 1.1 mv 3 mv 5.3 mv output rate (hz) -3 db filter frequency input range, (bipolar mode) 25 mv 55 mv 100 mv 1 v 2.5 v 5 v 1.88 1.64 16 17 18 18 18 18 3.76 3.27 16 17 17 17 18 18 7.51 6.55 15 16 17 17 17 17 15.0 12.7 15 16 16 16 16 16 30.0 25.4 14 14 14 14 14 14 61.6 (note 16) 50.4 12 12 12 12 12 12 84.5 (note 16) 70.7 10 10 10 10 10 10 101.1 (note 16) 84.6 8 8 8 8 8 8
cs5521/22/23/24/28 ds317f2 9 5 v digital characteristics (t a = 25 c; va+, vd+ = 5 v 5%; gnd = 0; see notes 2 and 18.)) notes: 18. all measurements performed under static conditions. 19. i out = -100 a unless stated otherwise. (v oh = 2.4 v @ i out = -40 a.) 3 v digital characteristics (t a = 25 c; va+ = 5 v 5%; vd+ = 3.0 v 10%; gnd = 0; see notes 2 and 18.) parameter symbol min typ max unit high-level input voltage all pins except xin and sclk xin sclk v ih 0.6 vd+ (vd+)-0.5 (vd+) - 0.45 - - - - - - v v v low-level input voltage all pins except xin and sclk xin sclk v il - - - - - - 0.8 1.5 0.6 v v v high-level output voltage all pins except cpd and sdo (note 19) cpd, i out = -4.0 ma sdo, i out = -5.0 ma v oh (va+) - 1.0 (vd+) - 1.0 (vd+) - 1.0 - - - - - - v v v low-level output voltage all pins except cpd and sdo, i out = 1.6 ma cpd, i out = 2 ma sdo, i out = 5.0 ma v ol - - - - - - 0.4 0.4 0.4 v v v input leakage current i in -110a 3-state leakage current i oz --10a digital output pin capacitance c out -9-pf parameter symbol min typ max unit high-level input voltage all pins except xin and sclk xin sclk v ih 0.6 vd+ (vd+)-0.5 (vd+) - 0.45 - - - - - - v v v low-level input voltage all pins except xin and sclk xin sclk v il - - - - - - 0.16 vd+ 0.3 0.6 v v v high-level output voltage all pins except cpd and sdo, i out = -400 a cpd, i out = -4.0 ma sdo, i out = -5.0 ma v oh (va+) - 0.3 (vd+) - 1.0 (vd+) - 1.0 - - - - - - v v v low-level output voltage all pins except cpd and sdo, i out = 400 a cpd, i out = 2 ma sdo, i out = 5.0 ma v ol - - - - - - 0.3 0.4 0.4 v v v input leakage current i in -110a 3-state leakage current i oz --10a digital output pin capacitance c out -9-pf
cs5521/22/23/24/28 10 ds317f2 dynamic characteristics recommended operating conditions (agnd, dgnd = 0 v; see note 20.) notes: 20. all voltages with respect to ground. absolute maximum ratings (agnd, dgnd = 0 v; see note 20.) notes: 21. no pin should go more negative than nbv - 0.3 v. 22. applies to all pins including continuous overvoltage conditions at the analog input (ain) pins. 23. transient current of up to 100 ma will not cause scr latch-up. maximum input current for a power supply pin is 50 ma. 24. total power dissipation, including all input currents and output currents. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameter symbol ratio unit modulator sampling frequency f s xin/4 hz filter settling time to 1/2 lsb (full scale step) t s 1/f out s parameter symbol min typ max unit dc power supplies positive digital positive analog vd+ va+ 2.7 4.75 5.0 5.0 5.25 5.25 v v analog reference voltage (vref+) - (vref-) vref diff 1.0 2.5 va+ v negative bias voltage nbv -1.8 -2.1 -2.5 v parameter symbol min typ max unit dc power supplies (note 21) positive digital positive analog vd+ va+ -0.3 -0.3 - - +6.0 +6.0 v v negative bias voltage negative potential nbv +0.3 -2.1 -3.0 v input current, any pin except supplies (note 22 and 23) i in --10ma output current i out --25ma power dissipation (note 24) pdn - - 500 mw analog input voltage vref pins ain pins v inr v ina nbv -0.3 nbv -0.3 - - (va+) + 0.3 (va+) + 0.3 v v digital input voltage v ind -0.3 - (vd+) + 0.3 v ambient operating temperature t a -40 - 85 c storage temperature t stg -65 - 150 c
cs5521/22/23/24/28 ds317f2 11 switching characteristics (t a = 25 c; va+ = 5 v 5%; vd+ = 3.0 v 10% or 5 v 5%; levels: logic 0 = 0 v, logic 1 = vd+; c l = 50 pf.)) notes: 25. device parameters are specified with a 32.768 khz clock; however, clocks up to 200 khz (cs5522/24/28) or 130 khz (cs5521/23) can be used for increased throughput. 26. specified using 10% and 90% points on waveform of interest. output loaded with 50 pf. 27. oscillator start-up time varies with crystal parameters. this specification does not apply when using an external clock source. 28. applicable when sclk is continuously running. specifications are subject to change without notice. parameter symbol min typ max unit master clock frequency (note 25) external clock or internal oscillator (cs5522/24/28) (cs5521/23) xin 30 30 32.768 32.768 200 130 khz khz master clock duty cycle 40 - 60 % rise times (note 26) any digital input except sclk sclk any digital output t rise - - - - - 50 1.0 100 - s s ns fall times (note 26) any digital input except sclk sclk any digital output t fall - - - - - 50 1.0 100 - s s ns start-up oscillator start-up time xtal = 32.768 khz (note 27) t ost -500-ms power-on reset period t por - 2006 - xin cycles serial port timing serial clock frequency sclk 0 - 2 mhz sclk falling to cs falling for continuous running sclk (note 28) t 0 100 - - ns serial clock pulse width high pulse width low t 1 t 2 250 250 - - - - ns ns sdi write timing cs enable to valid latch clock t 3 50 - - ns data set-up time prior to sclk rising t 4 50 - - ns data hold time after sclk rising t 5 100 - - ns sclk falling prior to cs disable t 6 100 - - ns sdo read timing cs to data valid t 7 --150ns sclk falling to new data bit t 8 --150ns cs rising to sdo hi-z t 9 --150ns
cs5521/22/23/24/28 12 ds317f2 cs sclk t 0 t 2 t 1 t 3 t 6 figure 1. continuous running sclk timing (not to scale) cs sclk msb msb-1 lsb sdi t 3 t 4 t 5 t 1 t 2 t 6 figure 2. sdi write timing (not to scale) cs sclk msb msb-1 lsb sdo t 7 t 8 t 1 t 2 t 9 figure 3. sdo read timing (not to scale)
cs5521/22/23/24/28 ds317f2 13 2. general description the cs5521/22/23/24/28 are highly integrated ds analog-to-digital converters (adcs) which use charge-balance techniques to achieve 16-bit (cs5521/23) and 24-bit (cs5522/24/28) perfor- mance. the adcs come as either two-channel (cs5521/22), four-channel (cs5523/24), or eight- channel (cs5528) devices, and include a low input current, chopper-stabilized instrumentation ampli- fier. to permit selectable input spans of 25 mv, 55 mv, 100 mv, 1 v, 2.5 v, and 5 v, the adcs in- clude a pga (programmable gain amplifier). to accommodate ground-based thermocouple applica- tions, the devices include a cpd (charge pump drive) which provides a negative bias voltage to the on-chip amplifiers. these devices also include a fourth order ds mod- ulator followed by a digital filter which provides eight selectable output word rates of 1.88 hz, 3.76 hz, 7.51 hz, 15 hz, 30 hz, 61.6 hz, 84.5 hz, and 101.1 hz (xin = 32.768 khz). the devices are capable of producing output update rates up to 617 hz when a 200 khz clock is used (cs5522/24/28) or up to 401 hz using a 130 khz clock (cs5521/23). further note that the digital fil- ters are designed to settle to full accuracy within one conversion cycle and simultaneously reject both 50 hz and 60 hz interference when operated at word rates below 30 hz (assuming a xin clock frequency of 32.768 khz). to ease communication between the adcs and a micro-controller, the converters include an easy to use three-wire serial interface which is spi? and microwire? compatible. 2.1 analog input figure 4 illustrates a block diagram of the analog in- put signal path inside the cs5521/22/23/24/28. the front end consists of a multiplexer (break before make configuration), a chopper-stabilized instru- mentation amplifier with fixed gain of 20x, coarse/fine charge buffers, and a programmable gain section. for the 25 mv, 55 mv, and 100 mv input ranges, the input signals are amplified by the 20x in- strumentation amplifier. for the 1 v, 2.5 v, and 5 v input ranges, the instrumentation amplifier is by- passed and the input signals are connected to the programmable gain block via coarse/fine charge buffers. vref+ differential 4th order delta- sigma modulator digital filter programmable gain vref- nbv x20 m u x ain2+ ain2- ain1+ ain1- cs5522 in+ in- ain4+ ain4- * * * ain1+ ain1- cs5524 ain8+ ain7+ * * * ain1+ cs5528 m u x m u x in+ in- in+ in- in+ in- figure 4. multiplexer configurations nbv also supplies the negative supply voltage for the coarse/fine change buffers
cs5521/22/23/24/28 14 ds317f2 2.1.1 instrumentation amplifier the instrumentation amplifier is chopper stabilized and is activated any time conversions are performed with the low level input ranges, 100 mv. the am- plifier is powered from va+ and from the nbv (negative bias voltage) pin allowing the cs5521/22/23/24/28 to be operated in either of two analog input configurations. the nbv pin can be bi- ased to a negative voltage between -1.8 v and - 2.5 v, or tied to agnd (for the cs5528, nbv has to be between -1.8 v and -2.5 v for the ranges below 100 mv when the amplifier is engaged). the com- mon-mode plus signal range of the instrumentation amplifier is 1.85 v to 2.65 v with nbv grounded. the common-mode plus signal range of the instru- mentation amplifier is -0.150 v to 0.950 v with nbv between -1.8 v to -2.5 v. whether nbv is tied between -1.8 v and -2.5 v or tied to agnd, the (common mode + signal) input on ain+ and ain- must stay between nbv and va+. figure 5 illustrates an analog input model for the adcs when the instrumentation amplifier is en- gaged. the cvf (sampling) input current for each of the analog input pins depends on the cfs1 and cfs0 (chop frequency select) bits in the configu- ration register (see configuration register for de- tails). note that the cvf current is lowest with the cfs bits in their default states (cleared to logic 0s). further note that the cvf current into the instru- mentation amplifier is less than 300 pa over -40c to +85c. note that figure 5 is for input current modeling only. for physical input capacitance see input capacitance specification under analog characteristics . also refer to applications note an30 switched-capacitor a/d converter input structures for more details on input models and input sampling currents. note: residual noise appears in the converters baseband for output word rates greater than 61.6 hz if the cfs bits are logic 0 (chop clock = 256 hz). for word rates of 30 hz and lower, 256 hz chopping is recommended, and for 61.6 hz, 84.5 hz and 101.1 hz filters, 4096 hz chopping is recommended. 2.1.2 coarse/fine charge buffers the unity gain buffers are activated any time conver- sions are performed with the high level inputs rang- es, 1 v, 2.5 v, and 5 v. the unity gain buffers are designed to accommodate rail to rail input signals. the common-mode plus signal range for the unity gain buffer amplifier is nbv to va+. typical cvf (sampling) current for the unity gain buffer amplifiers is about 10 na (xin = 32.768 khz, see figure 6). ain 25 mv, 55 mv, and 100 mv ranges c=48pf cfs1/cfs0 = 00, f = 256 hz cfs1/cfs0 = 01, f = 4096 hz cfs1/cfs0 = 10, f = 16.384 khz cfs1/cfs0 = 11, f = 1024 hz v 25 mv i=fv c os os n figure 5. input models for ain+ and ain- pins, (100 mv input ranges ain c = 20 pf f = 32.768 khz f coarse 1 f fine 1 v 25 mv i=fv c os os n 1 v, 2.5 v and 5 v ranges figure 6. input models for ain+ and ain- pins, >100 mv input ranges
cs5521/22/23/24/28 ds317f2 15 2.1.3 analog input span considerations the cs5521/22/23/24/28 is designed to measure full scale ranges of 25 mv, 55 mv, 100 mv, 1 v, 2.5 v and 5 v. other full scale values can be ac- commodated by performing a system calibration within the limits specified. see the calibration sec- tion for more details. another way to change the full scale range is to increase or to decrease the voltage reference to a voltage other than 2.5 . see the voltage reference section for more details. three factors set the operating limits for the input span. they include: instrumentation amplifier satu- ration, modulator 1s density, and a lower reference voltage. when the 25 mv, 55 mv or 100 mv range is selected, the input signal (including the common mode voltage and the amplifier offset voltage) must not cause the 20x amplifier to saturate in ei- ther its input stage or output stage. to prevent sat- uration the absolute voltages on ain+ and ain- must stay within the limits specified (refer to the analog input section). additionally, the differen- tial output voltage of the amplifier must not exceed 2.8 v. the equation abs(vin + vos) x 20 = 2.8 v defines the differential output limit, where vin = (ain+) - (ain-) is the differential input voltage and vos is the ab- solute maximum offset voltage for the instrumenta- tion amplifier (vos will not exceed 40 mv). if the differential output voltage from the amplifier ex- ceeds 2.8 v, the amplifier may saturate, which will cause a measurement error. the input voltage into the modulator must not cause the modulator to exceed a low of 20 percent or a high of 80 percent 1's density. the nominal full scale input span of the modulator (from 30 percent to 70 percent 1s density) is determined by the vref voltage divided by the gain factor. see table 1 to determine if the cs5521/22/23/24/28 are being used properly. for example, in the 55 mv range, to determine the nominal input volt- age to the modulator, divide vref (2.5 v) by the gain factor (2.2727). when a smaller voltage reference is used, the re- sulting code widths are smaller causing the con- verter output codes to exhibit more changing codes for a fixed amount of noise. table 1 is based upon a vref = 2.5 v. for other values of vref, the values in table 1 must be scaled accordingly. 2.1.4 measuring voltages higher than 5 v some systems require the measurement of voltages greater than 5 v. the input current of the instru- note: 1. the converter's actual input range, the delta-sigma's nominal full scale input, and the delta-sigma's maximum full scale input all scale directly with the value of the voltage reference. the values in the table assume a 2.5 v vref voltage. 2. the 2.8 v limit at the output of the 20x amplifier is the differential output voltage. input range (1) max. differential output 20x amplifier vref gain factor d - s nominal (1) differential input d - s (1) max. input 25 mv 2.8 v (2) 2.5v 5 0.5 v 0.75 v 55 mv 2.8 v (2) 2.5v 2.272727... 1.1 v 1.65 v 100 mv 2.8 v (2) 2.5v 1.25 2.0 v 3.0 v 1.0 v - 2.5v 2.5 1.0 v 1.5 v 2.5 v - 2.5v 1.0 2.5 v 5.0 v 5.0 v - 2.5v 0.5 5.0 v 0v, va+ table 1. relationship between full scale input, gain factors, and internal analog signal limitations
cs5521/22/23/24/28 16 ds317f2 mentation amplifier, typically 100 pa, is low enough to permit large external resistors to divide down a large external signal without significant loading. figure 7 illustrates an example circuit. re- fer to applications note 158 for more details on high voltage (>5 v) measurement. 2.1.5 voltage reference the cs5521/22/23/24/28 are specified for opera- tion with a 2.5 v reference voltage between the vref+ and vref- pins of the device. for a single- ended reference voltage, such as the lt1019-2.5, the reference voltage is input into the vref+ pin of the converter and the vref- pin is grounded. the differential voltage between the vref+ and vref- can be any voltage from 1.0 v up to va+, however, the vref+ cannot go above va+ and the vref- pin can not go below nbv. figure 8 illustrates the input models for the vref pins. the dynamic input current for each of the pins can be determined from the models shown. 2.2 overview of adc register structure and operating modes the cs5521/22/23/24/28 adcs have an on-chip controller, which includes a number of user-acces- sible registers. the registers are used to hold offset and gain calibration results, configure the chip's operating modes, hold conversion instructions, and to store conversion data words. figure 9 depicts a block diagram of the on-chip controllers internal registers for the cs5523/24. each of the converters has 24-bit registers to func- tion as offset and gain calibration registers for each channel. the converters with two channels have two offset and two gain calibration registers, the converters with four channels have four offset and four gain calibration registers, and the eight chan- nel converter has eight offset and eight gain cali- bration registers. these registers hold calibration results. the contents of these registers can be read or written by the user. this allows calibration data to be off-loaded into an external eeprom. the user can also manipulate the contents of these reg- isters to modify the offset or the gain slope of the converter. the converters include a 24-bit configuration reg- ister of which 17 of the bits are used for setting op- tions such as the conversion mode, operating power options, setting the chop clock rate of the instru- mentation amplifier, and providing a number of flags which indicate converter operation. voltage divider pgia set for + 100 mv 10v charge pump regulator ds adc pgia +5 v 2.5 v va+ vref+ vref- vd+ + - nbv v ? -2.1 v + 10 m f 0.033 m f cpd 0.1 m f 10 w 0.1 m f 1n4148 1n4148 bat85 charge pump circuitry dgnd chop clock = 256 hz 10 k w 1 m w figure 7. input ranges greater than 5 v vref c = 10pf f = 32.768 khz 2 f fine 1 v 25mv i = fv c os os n f coarse figure 8. input model for vref+ and vref- pins
cs5521/22/23/24/28 ds317f2 17 a group of registers, called channel set-up regis- ters, are also included in the converters. these reg- isters are used to hold pre-loaded conversion instructions. each channel set-up register is 24 bits long and holds two 12-bit conversion instructions (setups). upon power up, these registers can be ini- tialized by the users' microcontroller with conver- sion instructions. the user can then use bits in the configuration register to choose a conversion mode. several conversion modes are possible. using the single conversion mode, an 8-bit command word can be written into the serial port. the command in- cludes pointer bits which point to a 12-bit com- mand in one of the channel setup registers which is to be executed. the 12-bit commands can be set- up to perform a conversion on any of the input channels of the converter. more than one of the 12- bit setups can be used for the same analog input channel. this allows the user to convert on the same signal with either a different conversion speed, a different gain range, or any of the other op- tions available in the setup register. the user can set up the registers to perform different conversion conditions on each of the input channels. the adcs also include multiple channel conver- sion capability. user bits in the configuration regis- ter of the adcs can be configured to sequence through the 12-bit command setups, performing a conversion according to the content of each 12-bit setup. this channel scanning capability can be configured to run continuously, or to scan through a specified number of setup registers and stop un- til commanded to continue. in the multiple channel scanning modes, the conversion data words are loaded into an on-chip data fifo. the converter is- sues a flag on the sdo pin when a scan cycle is completed so the user can read the fifo. more de- tails are given in the following pages. instructions are provided to initialize the converter, perform offset and gain calibrations, and how to configure the converter for the various conversion modes. each of the bits of the configuration regis- ter and of the channel setup registers is described. a list of examples follows the description section. table 2 can be used to decode all valid commands (the first 8-bits into the serial port). ain1 ain2 ain3 ain4 4 (24) 4 (24) 4 (12 x 2) 8 x 24 off 1 off 2 off 3 off 4 gain 1 gain 2 gain 3 gain 4 setup 1 setup 3 setup 5 setup 7 setup 2 setup 4 setup 6 setup 8 data fifo sdo 1 x 24 configuration chop frequency multiple conversions depth pointer loop read convert powerdown modes flags etc. latch outputs channel select output word rate pga selection unipolar/bipolar figure 9. cs5523/24 register diagram
cs5521/22/23/24/28 18 ds317f2 2.2.1 system initialization when power to the cs5521/22/23/24/28 is applied, the chips are held in a reset condition until the 32.768 khz oscillator has started and a counter- timer elapses. due to the high q of the 32.768 khz crystal, the oscillator takes 400-600 ms to start. the counter-timer counts 2006 oscillator clock cycles to make sure the oscillator is fully stable. during this time-out period the serial port logic is reset and the rv (reset valid) bit in the configuration regis- ter is set to indicate that a valid reset occurred. af- ter a reset, the on-chip registers are initialized to the following states and the converter is placed in the command mode where it waits for a valid com- mand. note: a system reset can be initiated at any time by writing a logic 1 to the rs (reset system) bit in the configura- tion register. after a reset, the rv bit is set until the configuration register is read. the user must then write a logic 0 to the rs bit to take the part out of the reset mode. any other bits written to the configuration register at this time will be lost. the configuration reg- ister must be written again once rs = 0 to set any other bits. 2.2.2 serial port initialization sequence the serial port is initialized to the command mode whenever a power-on reset is performed inside the converter, or when the user transmits the port ini- tialization sequence. the port initialization se- quence involves clocking 15 bytes of all 1's, followed by one byte with the following bit con- tents 11111110. this sequence places the chip in the command mode where it waits for a valid com- mand to be written. configuration register: 000040(h) offset registers: 000000(h) gain registers: 400000(h) channel setup registers: 000000(h)
cs5521/22/23/24/28 ds317f2 19 2.2.3 command register quick reference d7(msb)d6d5d4d3d2d1d0 cb cs2 cs1 cs0 r/w rsb2 rsb1 rsb0 bit name value function d7 command bit, cb 0 1 must be logic 0 for these commands. see table below. d6-d4 channel select bits, csb2-csb0 000 . . 111 cs2-cs0 provide the address of one of the eight physical channels. these bits are used to access the calibration regis- ters associated with respective channels. note: these bits are ignored when reading the data register. d3 read/write , r/w 0 1 write to selected register. read from selected register. d2-d0 register select bit, rsb2-rsb0 000 001 010 011 101 110 111 reserved offset register gain register configuration register channel set-up registers - register is 48-bits long for cs5521/22 - register is 96-bits long for cs5523/24 - register is 192-bits long for cs5528 reserved reserved d7(msb)d6d5d4d3d2d1d0 cb csrp3 csrp2 csrp1 csrp0 cc2 cc1 cc0 bit name value function d7 command bit, cb 0 1 see table above. must be logic 1 for these commands. d6-d3 channel pointer bits, csrp3-csrp0 0000 . . . 1111 these bits are used as pointers to the setups. note: the mc bit, must be logic 0 for these bits to take effect. when mc = 1, these bits are ignored. the lp, mc, and rc bits in the configuration register are ignored during calibra- tion. d2-d0 conversion/calibration bits, cc2-cc0 000 001 010 011 100 101 110 111 normal conversion self-offset calibration self-gain calibration reserved reserved system-offset calibration system-gain calibration reserved table 2. command register quick reference
cs5521/22/23/24/28 20 ds317f2 2.2.4 command register descriptions read/write individual offset calibration register function : these commands are used to access each offset register separately. cs1 - cs0 decode the registers accessed. r/w (read/write) 0 write to selected register. 1 read from selected register. cs[2:0] (channel select bits) 000 offset register 1(all devices) 001 offset register 2 (all devices) 010 offset register 3 (cs5523/24/28 only) 011 offset register 4 (cs5523/24/28 only) 100 offset register 5 (cs5528 only) 101 offset register 6 (cs5528 only) 110 offset register 7 (cs5528 only) 111 offset register 8 (cs5528 only) read/write individual gain register function : these commands are used to access each gain register separately. cs1 - cs0 decode the reg- isters accessed. r/w (read/write) 0 write to selected register. 1 read from selected register. cs[2:0] (channel select bits) 000 gain register 1(all devices) 001 gain register 2 (all devices) 010 gain register 3 (cs5523/24/28 only) 011 gain register 4 (cs5523/24/28 only) 100 gain register 5 (cs5528 only) 101 gain register 6 (cs5528 only) 110 gain register 7 (cs5528 only) 111 gain register 8 (cs5528 only) d7(msb)d6d5d4d3d2d1d0 0 cs2 cs1 cs0 r/w 001 d7(msb)d6d5d4d3d2d1d0 0 cs2 cs1 cs0 r/w 010
cs5521/22/23/24/28 ds317f2 21 read/write configuration register function: these commands are used to read from or write to the configuration register. r/w (read/write) 0 write to selected register. 1 read from selected register. read/write channel-setup register(s) function : these commands are used to access the channel-setup registers (csrs). the number of csrs accessed is determined by the device being used and the number of csrs that are being accessed (i.e. the depth bits in the configuration register determine the number of levels ac- cessed). this register is 48-bits long (4 setups) for the cs5521/22, 96-bits long (8 setups) for the cs5523/24, and 192-bits (16 setups) long for the cs5528. r/w (read/write) 0 write to selected register. 1 read from selected register. d7(msb)d6d5d4d3d2d1d0 0000r/w 011 d7(msb)d6d5d4d3d2d1d0 0000r/w 101
cs5521/22/23/24/28 22 ds317f2 perform conversion function: these commands instruct the adc to perform conversions on the physical input channel point- ed to by the pointer bits (csrp2 - csrp0) in the channel-setup registers. the particular type of conversion performed is determined by the states of the conversion control bits (the multiple conversion bit, the loop bit, read convert bit, and the depth pointer bits) in the configuration reg- ister. csrp [3:0] (channel setup register pointer bits) 0000 setup 1 (all devices) 0001 setup 2 (all devices) 0010 setup 3 (all devices) 0011 setup 4 (all devices) 0100 setup 5 (cs5523/24/28) 0101 setup 6 (cs5523/24/28) 0110 setup 7 (cs5523/24/28) 0111 setup 8 (cs5523/24/28) 1000 setup 9 (cs5528 only) 1001 setup 10 (cs5528 only) 1010 setup 11 (cs5528 only) 1011 setup 12 (cs5528 only) 1100 setup 13 (cs5528 only) 1101 setup 14 (cs5528 only) 1110 setup 15 (cs5528 only) 1111 setup 16 (cs5528 only) d7(msb)d6d5d4d3d2d1d0 1 csrp3 csrp2 csrp1 csrp0 0 0 0
cs5521/22/23/24/28 ds317f2 23 perform calibration function: these commands instruct the adc to perform a calibration on the physical input channel refer- enced which is chosen by the command byte pointer bits (csrp3 - crsp0). csrp [3:0] (channel setup register pointer bits) 0000 setup 1 (all devices) 0001 setup 2 (all devices) 0010 setup 3 (all devices) 0011 setup 4 (all devices) 0100 setup 5 (cs5523/24/28 only) 0101 setup 6 (cs5523/24/28 only) 0110 setup 7 (cs5523/24/28 only) 0111 setup 8 (cs5523/24/28 only) 1000 setup 9 (cs5528 only) 1001 setup 10 (cs5528 only) 1010 setup 11 (cs5528 only) 1011 setup 12 (cs5528 only) 1100 setup 13 (cs5528 only) 1101 setup 14 (cs5528 only) 1110 setup 15 (cs5528 only) 1111 setup 16 (cs5528 only) cc [2:0] (calibration control bits) 000 reserved 001 self-offset calibration 010 self-gain calibration 011 reserved 100 reserved 101 system-offset calibration 110 system-gain calibration 111 reserved d7(msb)d6d5d4d3d2d1d0 1 csrp3 csrp2 csrp1 csrp0 cc2 cc1 cc0
cs5521/22/23/24/28 24 ds317f2 sync1 function: part of the serial port re-initialization sequence. sync0 function: end of the serial port re-initialization sequence. null function: this command is used to clear a port flag and keep the converter in the continuous conversion mode. d7(msb)d6d5d4d3d2d1d0 11111111 d7(msb)d6d5d4d3d2d1d0 11111110 d7(msb)d6d5d4d3d2d1d0 00000000
cs5521/22/23/24/28 ds317f2 25 2.2.5 serial port interface the cs5521/22/23/24/28s serial interface consists of four control lines: cs , sclk, sdi, sdo. figure 10 illustrates the serial sequence necessary to write to, or read from the serial ports registers. cs , chip select, is the control line which enables access to the serial port. if the cs pin is tied low, the port can function as a three wire interface. sdi, serial data in, is the data signal used to trans- fer data to the converters. sdo, serial data out, is the data signal used to transfer output data from the converters. the sdo output will be held at high impedance any time cs is at logic 1. sclk, serial clock, is the serial bit-clock which controls the shifting of data to or from the adcs serial port. the cs pin must be held low (logic 0) before sclk transitions can be recognized by the port logic. to accommodate optoisolators sclk is designed with a schmitt-trigger input to allow an optoisolator with slower rise and fall times to di- rectly drive the pin. additionally, sdo is capable of sinking or sourcing up to 5 ma to directly drive an optoisolator led. sdo will have less than a 400 mv loss in the drive voltage when sinking or sourcing 5 ma. command time 8sclks data time 24 sclks write cycle cs sclk sdi msb lsb command time 8sclks cs sclk sdi data time 24 sclks sdo msb lsb read cycle command time 8 sclks 8 sclks clear sdo flag sdo sclk sdi data time 24 sclks msb lsb * td = xin/owr clock cycles for each conversion except the first conversion which will take xin/owr + 7 clock cycles xin/owr clock cycles t * d figure 10. command and data word timing
cs5521/22/23/24/28 26 ds317f2 2.2.6 reading/writing the offset, gain, and configuration registers the cs5521/22/23/24/28s offset, gain, and config- uration registers are accessed individually and can be read from or written to. to write to an offset, a gain, or the configuration register, the user must transmit the appropriate write command which ac- cesses the particular register and then follow that command by 24 bits of data (refer to figure 10 for details). for example, to write 0x800000 (hexadeci- mal) to physical channel ones gain register, the user would transmit the command byte 0x02 (hexadeci- mal) and then follow that command byte with the data 0x800000 (hexadecimal). similarly, to read physical channel ones gain register, the user must first transmit the command byte 0x0a (hexadeci- mal) and then read the 24 bits of data. once an off- set, a gain, or the configuration register is written to or read from, the serial p ort returns to the command mode. 2.2.7 r eading/writing the channel-setup reg- i sters the cs5521/22 have two 24-bit channel-setup reg- isters (csrs). the cs5523/24 have four csrs, and the cs5528 has eight csrs (refer to table 3 for more detail on the csrs). these registers are ac- cessed in conjunction with the depth pointer bits in the configuration register. each csr contains two 12-bit setups which are programmed by the user to contain data conversion or calibration information such as: 1) state of the output latch pins 2) output word rate 3) gain range 4) polarity 5) the address of a physical input channel to be converted. once programmed they are used to determine the mode (e.g. unipolar, 15 hz, 100 mv range etc.) the adc will operate in when future conversions or calibrations are performed. to access the csrs, the user must first initialize the depth pointer bits in the configuration register as these bits determine the number of csrs to read from or write to. for example, to write csr1 (setup1 and setup2), the user would first program the configuration registers depth pointer bits with 0001 binary. this notifies the adcs serial port that only the first csr is to be accessed. then, the user would transmit the write command, 0x05 (hexadecimal) and follow that command with 24- bits of data. similarly, to read csr1, the user must transmit the command byte 0x0d (hexadecimal) and then read the 24 bits of data. to write more than one csr, for instance csr1 and csr2 (setup1, setup2, setup3 and setup4), the user would first set the depth pointer bits in the configuration register to 0011 binary. the user would then trans- mit the write csr command 0x05 (hexadecimal) and follow that with the information for setup1, setup2, setup 3, and setup 4 which is 48-bits of in- formation. note that while reading/writing csrs, two setups are accessed in pairs as a single 24-bit csr register. even if one of the setups isnt used, it must be written to or read. further note that the csrs are accessed as a closed array, the user can not access csr2 without accessing csr1. this re- quirement means that the depth bits in the configu- ration register can only be set to one of the following states when the csrs are being read from or written to: 0001, 0011, 0101, 0111, 1001, 1011, 1101, 1111. examples detailing the power of the csrs are pro- vided in the performing conversions and reading the data conversion fifo section. once the csrs are written to or read from, the serial port returns to the command mode.
cs5521/22/23/24/28 ds317f2 27 * r indicates the bit value after the part is reset csr (channel-setup register) csr csr #1 lc (log. channel) 1 bits <47:36> lc 2 bits <35:24> #1 lc 1 bits <95:84> lc 2 bits <83:72> #1 lc 1 bits <191:180> lc 2 bits <179:168> #2 lc 3 bits <23:12> lc 4 bits <11:0> #4 lc 7 bits <23:12> lc 8 bits <11:0> #8 lc 15 bits <23:12> lc 16 bits <11:0> cs5521/22 cs5523/24 cs5528 d23(msb) d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 a1 a0 cs2 cs1 cs0 wr2 wr1 wr0 g2 g1 g0 u/b d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a1 a0 cs2 cs1 cs0 wr2 wr1 wr0 g2 g1 g0 u/b bit name value function d23-d22/ d11-d10 latch outputs, a1-a0 00 *r latch output pins a1-a0 mimic d23/d11-d22/d10 register bits. d21-d19/ d9-d7 channel select, cs2- cs0 000 001 010 011 100 101 110 111 r select physical channel 1 (all devices) select physical channel 2(all devices) select physical channel 3 (cs5523/24/28 only) select physical channel 4 (cs5523/24/28 only) select physical channel 5 (cs5528 only) select physical channel 6 (cs5528 only) select physical channel 7 (cs5528 only) select physical channel 8 (cs5528 only) d18-d16/ d6-d4 word rate, wr2-wr0 000 001 010 011 100 101 110 111 r 15.0 hz (2180 xin cycles). 30.0 hz (1092 xin cycles). 61.6 hz (532 xin cycles). 84.5 hz (388 xin cycles). 101.1 hz (324 xin cycles). 1.88 hz (17444 xin cycles). 3.76 hz (8724 xin cycles). 7.51 hz (4364 xin cycles). d15-d13/ d3-d1 gain bits, g2-g0 000 001 010 011 100 101 110 111 r 100 mv (assumes vref differential = 2.5 v) 55 mv 25 mv 1.0 v 5.0 v 2.5 v not used. not used. d12/d0 unipolar/bipolar, u/b 0 1 r bipolar measurement mode. unipolar measurement mode. table 3. channel-setup registers
cs5521/22/23/24/28 28 ds317f2 2.2.7.1 latch outputs the a1-a0 pins mimic the latch output, d23/d11- d22/d10, bits of the channel-setup registers. a1-a0 can be used to control external multiplexers and oth- er logic functions outside the converter. the outputs can sink or source at least 1 ma, but it is recom- mended to limit drive currents to less than 20 m a to reduce self-heating of the chip. t hese outputs are powered from va+, hence, their output voltage for a logic 1 will be limited to the va+ supply voltage. 2.2.7.2 channel select bits the channel select, cs1-cs0, bits are used to de- termine which physical input channel will be used when a conversion is performed with a particular setup. 2.2.7.3 output word rate selection the word rate, wr2-wr0, bits of the channel-set- up registers set the output conversion word rate of the converter when a conversion is performed with a particular setup. the word rates indicated in table 3 assume a master clock of 32.768 khz, and scale linearly when using other master clock fre- quencies. upon reset the converter is set to operate with an output word rate of 15.0 hz. 2.2.7.4 gain bits the gain bits, g2-g0, of the channel-setup regis- ters set the full scale differential input range for the adc when a conversion is performed with a partic- ular setup. the input ranges in the table assume a 2.5 v reference voltage, and scale linearly when using other reference voltages. 2.2.7.5 unipolar/bipolar bit the unipolar/bipolar bit is used to determine the type of conversion, unipolar/bipolar, that will be performed with a particular setup. 2.2.8 configuration register the configuration register is 24-bits long. the fol- lowing subsections detail the bits in the configura- tion register. table 4 summarizes the configuration register. 2.2.8.1 chop frequency select the chop frequency select (cfs1-cfs0) bits are used to set the rate at which the instrumentation amplifiers chop switches modulate the input sig- nal. the 256 hz rate is desirable as it provides the lowest input cvf (sampling) current, <300 pa over -40 to 85 c. the higher rates can be used to eliminate modulation/aliasing effects as the fre- quency of the input signal increases. 2.2.8.2 conversion/calibration control bits the conversion/calibration control bits in the con- figuration register are used to control the particular type of conversion required for the users applica- tions. in short, the depth pointer (dp3-dp0) bits determine the number of setups that will be refer- enced when conversions are performed. the multi- ple conversion (mc) bit instructs the converter to perform conversions on the number of setups in the channel-setup registers which are referenced by the depth pointer bits. the converter begins with setup1 and moves sequentially through the setups in this mode. the loop (lp) bit instructs the con- verter to continuously perform conversions until a stop command is sent to the converter. the read convert (rc) bit instructs the converter to wait until the conversion data is read before performing the next conversion or set of conversions. 2.2.8.3 power consumption control bits the cs5522/24/28 accommodate four power con- sumption modes: normal, low power, standby, and sleep. the cs5521/23 accommodate three power consumption modes: normal, standby, and sleep. the normal (default) mode is entered after a power- on-reset. in normal mode, the cs5522/24/28 typi-
cs5521/22/23/24/28 ds317f2 29 cally consume 9.0 mw. the cs5521/23 typically consume 5.5 mw. the low power mode is an alter- nate mode in the cs5522/24/28 that reduces the consumed power to 5.5 mw. it is entered by setting bit d8 (the low power mode bit) in the configura- tion register to logic 1. slightly degraded noise or linearity performance should be expected in the low power mode. note that the xin clock should not exceed 130 khz in low power mode. the final two modes accommodated in all devices are re- ferred to as the power save modes. they power down most of the analog portion of the chip and stop filter convolutions. the power save modes are entered whenever the ps/r bit of the configuration register is set to logic 1. the particular power save mode entered depends on state of bit d11 (pss, the power save select bit) in the configuration register. if pss is logic 0, the converters enters the standby mode reducing the power consumption to 1.2 mw. the standby mode leaves the oscillator and the on- chip bias generator running. this allows the con- verter to quickly return to the normal or low power mode once the ps/r bit is set back to a logic 1. if pss and ps/r in the configuration register are set to logic 1, the sleep mode is entered reducing the consumed power to around 500 m w. since the sleep mode disables the oscillator, approximately a 500ms oscillator start-up delay period is required before returning to the normal or low power mode. 2.2.8.4 charge pump disable the pump disable (pd) bit permits the user to turn off the charge pump drive thus enabling the user to reduce the radiation of digital interference from the cpd pin when the charge pump is not being used. 2.2.8.5 reset system control bits the reset system (rs) bit permits the user to per- form a system reset. a system reset can be initiated at any time by writing a logic 1 to the rs bit in the configuration register. after a system reset cycle is complete, the reset valid (rv) bit is set indicating that the internal logic was properly reset. the rv remains set until the configuration register is read. note that the user must write a logic 0 to the rs bit to take the part out of the reset mode. no other bits in the configuration register can be written at this time. a subsequent write to the configuration reg- ister is necessary to write to any other bits in this register. once reset, the on-chip registers are ini- tialized to the following states. 2.2.8.6 data conversion error flags the oscillation detect (od) and over flow (of) bits in the configuration register are flag bits used to in- dicate that the adc performed a conversion on an input signal that was not within the conversion range of the adc. for convenience, the od and of bits are also in the data conversion word of the cs5521/23. the of bit is set to logic 1 when the input signal is: 1) more positive than full scale 2) more negative than zero in unipolar mode, or 3) more negative than negative full scale in bipo- lar mode. the of flag is cleared to logic 0 when a conversion occurs which is not out of range. the od bit is set to logic 1 any time that an oscil- latory condition is detected in the modulator. this does not occur under normal operating conditions, but may occur when the input is extremely over- ranged. the od flag will be cleared to logic 0 when the modulator becomes stable. configuration register: 000040(h) offset registers: 000000(h) gain registers: 400000(h) channel setup registers: 000000(h)
cs5521/22/23/24/28 30 ds317f2 * r indicates the bit value after the part is reset d23(msb) d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 nu nu cfs1 cfs0 nu mc lp rc dp3 dp2 dp1 dp0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 pss pd ps/r lpmrs rv od ofnunununu bit name value function d23-d22 not used, nu 00 r* must always be logic 0. d21-d20 chop frequency select, cfs1-cfs0 00 01 10 11 r 256 hz amplifier chop frequency. (xin = 32.768 khz) 4,096 hz amplifier chop frequency. 16,384 hz amplifier chop frequency. 1,024 hz amplifier chop frequency. d19 not used, nu 0 r must always be logic 0. d18 multiple conversion, mc 0 1 r perform single-setup conversions. mc bit is ignored during calibrations. perform multiple-setup conversions on setups in the channel-setup reg- ister by issuing only one command with msb = 1. d17 loop, lp 0 1 r the conversions on the single setup (mc = 0) or multiple setups (mc = 1) are performed only once. the conversions on the single setup (mc = 0) or multiple setups (mc = 1) are continuously performed. d16 read convert, rc 0 1 r dont wait for user to finish reading data before starting new conversions. the rc bit is used in conjunction with the lp bit when the lp bit is set to logic 1. if lp = 0, the rc bit is ignored. if lp = 1, the adc waits for user to read data conversion(s) before converting again. the rc bit is ignored during calibrations. refer to calibration protocol for details. d15-d12 depth pointer, dp3-dp0 0000 . . 1111 r when writing or reading the csrs, these bits (dp3-dp0) determine the number of csrs to be accessed. they are also used to determine how many setups are converted when mc=1 and a command byte with its msb = 1 is issued. note that the cs5522 has two csrs, the cs5524 has four csrs, and the cs5528 has 8 csrs. d11 power save select, pss 0 1 r standby mode (oscillator active, allows quick power-up). sleep mode (oscillator inactive). d10 pump disable, pd 0 1 r charge pump enabled. for pd = 1, the cpd pin goes to a hi-z output state. d9 power save/run , ps/r 0 1 rrun. power save. d8 low power mode, lpm 0 1 r normal mode (lpm bit is only for the cs5522/24/28) reduced power mode d7 reset system, rs 0 1 r normal operation. activate a reset cycle. to return to normal operation write bit to zero. d6 reset valid, rv 0 1r no reset has occurred or bit has been cleared (read only). bit is set after a valid reset has occurred. (cleared when read.) d5 oscillation detect, od 0 1 r bit is clear when an oscillation condition has not occurred (read only). bit is set when an oscillatory condition is detected in the modulator. d4 overrange flag, of 0 1 r bit is clear when an overrange condition has not occurred (read only). bit is set when input signal is more positive than the positive full scale, more negative than zero (unipolar mode), or when the input is more neg- ative than the negative full scale (bipolar mode). d3-d0 not used, nu 0000 r must always be logic 0. table 4. configuration register
cs5521/22/23/24/28 ds317f2 31 2.3 calibration the cs5521/22/23/24/28 offer four different cali- bration functions including self calibration and sys- tem calibration. however, after the devices are reset, the converter is functional and can perform measurements without being calibrated. in this case, the converter will utilize the initialized values of the on-chip registers (gain = 1.0, offset = 0.0) to calculate output words for the 100 mv range. any initial offset and gain errors in the internal cir- cuitry of the chip will remain. the gain and offset registers, which are used for both self and system calibration, are used to set the zero and full-scale points of the converters transfer function. one lsb in the offset register is 2 -24 pro- portion of the input span when the gain register is set to 1.0 decimal (bipolar span is 2 times the uni- polar span). the msb in the offset register deter- mines if the offset to be trimmed is positive or negative (0 positive, 1 negative). the converter can typically trim 50 percent of the input span. the gain register spans from 0 to (4 - 2 -22 ). the decimal equivalent meaning of the gain register is: where the binary numbers have a value of either zero or one (b 0 corresponds to bit msb-1, n=22). refer to table 5 for details. the offset and gain calibration steps each take one conversion cycle to complete. at the end of the cal- ibration step, sdo falls to indicate that the calibra- tion has finished. 2.3.1 self calibration the cs5521/22/23/24/28 offer both self offset and self gain calibrations. for the self-calibration of offset in the 25 mv, 55 mv, and 100 mv ranges, the converters internally tie the inputs of the instru- mentation amplifier together and route them to the ain- pin as shown in figure 11 (in the cs5528 they are routed to agnd). for proper self-calibra- table 5. offset and gain registers offset register one lsb represents 2 -24 proportion of the input span when gain register is set to 1.0 decimal (bipolar span is 2 times unipolar span) offset and data word bits align by msb (bit msb-4 of offset register changes bit msb-4 of data) gain register the gain register span is from 0 to (4-2 -22 ). after reset the (msb-1) bit is 1, all other bits are 0. msb lsb register sign 2 -2 2 -3 2 -4 2 -5 2 -6 2 -19 2 -20 2 -21 2 -22 2 -23 2 -24 reset (r) 000000 000000 msb lsb register 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 reset (r) 010000 000000 ? ? db msb 2 1 b ( 0 2 0 b 1 2 1 C ? b n 2 n C ) ++++ b msb 2 1 b i 2 i C i 0 = n ? + ==
cs5521/22/23/24/28 32 ds317f2 tion of offset to occur in the 25 mv, 55 mv, and 100 mv ranges, the ain- pin must be at the proper common-mode-voltage as specified in common mode +signal ain+/- specification in the analog input section (if ain- = 0 v, nbv must be between -1.8 v to -2.5 v). for self-calibration of offset in the 1.0 v, 2.5 v, and 5 v ranges, the inputs of the mod- ulator are connected together and then routed to the vref- pin as shown in figure 12. for self-calibration of gain, the differential inputs of the modulator are connected to vref+ and vref- as shown in figure 13. for any input range other than the 2.5 v range, the converters gain er- ror can not be completely calibrated out when using self-calibration. this is due to the lack of an accu- rate full scale voltage internal to the chips. the 2.5 v range is an exception because the external reference voltage is 2.5 v nominal and is used as the full scale voltage. in addition, when self-cali- bration of gain is performed in the 25 mv, 55 mv, and 100 mv input ranges, the instrumentation am- plifiers gain is not calibrated. these two factors can leave the converters with a gain error of up to 20% after self-calibration of gain. therefore, a system gain calibration is required to get better ac- curacy, except for the 2.5 v range. 2.3.2 system calibration for the system calibration functions, the user must supply the calibration signals to the converter which represent ground and full scale. when a system offset calibration is performed, a ground referenced signal must be applied to the converters. see figures 14 and 15. as shown in figures 16 and 17, the user must input a signal representing the positive full scale point to ain+ ain- s1 open s2 closed + - x20 + - figure 11. self calibration of offset (low ranges) ain+ ain- s1 open + - x20 + - s2 open s4 closed vref- s3 closed figure 12. self calibration of offset (high ranges) ain+ ain- open + - x20 + - open closed vref+ closed vref- + - reference figure 13. self calibration of gain (all ranges) + - x20 + - external connections 0v + - ain+ ain- cm + - figure 14. system calibration of offset (low ranges)
cs5521/22/23/24/28 ds317f2 33 perform a system gain calibration. in either case, the calibration signals must be within the specified calibration limits for each specific calibration step (refer to the system calibration specifications in analog characteristics ). if a system gain calibration is performed the following conditions must be met: 1) full-scale input must not saturate the 20x in- strumentation amplifier, if the calibration is on an input range where the instrumentation am- plifier is involved. 2) the 1s density of the modulator must not be greater than 80 percent (the input to the ds modulator must not exceed the maximum input which table 1 specifies). 3) the input must not be so small relative to the range chosen that the resulting gain registers content, decoded in decimal, exceeds 3.9999998 (see the discussion of operating lim- its on input span under the analog input and limitations in calibration range sections). this requires the full scale input voltage to the modulator to be at least 25 percent of the nom- inal value. the converters input ranges were chosen to guar- antee gain calibration accuracy to 1 lsb 16 or 16 lsb 24 when system gain calibration is performed. this is useful when a user wants to manually scale the full scale range of the converter and maintain accuracy. for example, if a gain calibration is per- formed with a 2.5 v full scale voltage and a 1.25 v input range is desired, the user can read the con- tents of the gain register, shift the register contents left by 1 bit, and then write the result back to the gain register. this multiples the gain by 2. assuming a system can provide two known voltag- es, the following equations allow the user to manu- ally compute the calibration registers values based on two uncalibrated conversions (see note). the offset and gain calibration registers are used to ad- just a typical conversion as follows: rc = (ru + co) * cg / 2 22 . calibration can be performed using the following equations: co = (rc0/g - ru0) cg = 2 22 * g where g = (rc1 - rc0)/(ru1-ru0). note: uncalibrated conversions imply that the gain and off- set registers are at default {gain register = 0x400000 (hex) and offset register = 0x000000 (hex)}. + - x20 + - external connections + - ain+ ain- cm + - 0v figure 15. system calibration of offset (high ranges) + - x20 + - external connections full scale + - ain+ ain- cm + - figure 16. system calibration of gain (low ranges) + - x20 + - external connections full scale + - ain+ ain- cm + - figure 17. system calibration of gain (high ranges)
cs5521/22/23/24/28 34 ds317f2 the variables are defined below. v0 = first calibration voltage v1 = second calibration voltage (greater than v0) ru = result of any uncalibrated conversion ru0 = result of uncalibrated conversion v0 (24- bit integer or 2s complement) ru1 = result of uncalibrated conversion of v1 (24-bit integer or 2s complement) rc = result of any conversion rc0 = desired calibrated result of converting v0 (24-bit integer or 2s complement) rc1 = desired calibrated result of converting v1 (24-bit integer or 2s complement) co = offset calibration register value (24-bit 2s complement) cg = gain calibration register value (24-bit integer) 2.3.3 calibration tips calibration steps are performed at the output word rate selected by the wr2-wr0 bits of the configu- ration register. since higher word rates result in conversion words with more peak-to-peak noise, calibration should be performed at lower output word rates. also, to minimize digital noise near the device, the user should wait for each calibration step to be completed before reading or writing to the serial port. for maximum accuracy, calibrations should be per- formed for offset and gain (selected by changing the g2-g0 bits of the desired setup). note that only one gain range can be calibrated per physical chan- nel. i f factory calibration of the users system is performed using the system calibration capabilities of the cs5521/22/23/24/28, the offset and gain reg- ister contents can be read by the system microcon- troller and recorded in eeprom. these same calibration words can then be uploaded into the off- set and gain registers of the converter when power is first applied to the system, or when the gain range is changed. 2.3.4 limitations in calibration range system calibration can be limited by signal head- room in the analog signal path inside the chip as discussed under the analog input section of this data sheet. for gain calibration the full scale input signal can be reduced to the point in which the gain register reaches its upper limit of (4-2 -22 decimal) or ffffff (hexadecimal). under nominal condi- tions, this occurs with a full scale input signal equal to about 1/4 the nominal full scale. with the con- verters intrinsic gain error, this full scale input sig- nal may be higher or lower. in defining the minimum full scale calibration range (fscr) under analog characteristics , margin is retained to accommodate the intrinsic gain error. alternatively the input full scale signal can be in- creased to a point in which the modulator reaches its 1s density limit of 80 percent, which under nominal condition occurs when the full scale input signal is 1.5 times the nominal full scale. with the chips intrinsic gain error, this full scale input sig- nal may be higher or lower. in defining the maxi- mum fscr, margin is again incorporated to accommodate the intrinsic gain error. in addition, for full scale inputs greater than the nominal full scale value of the range selected, there is some volt- age at which various internal circuits may saturate due to limited amplifier headroom. this is most likely to occur in the 100 mv range. 2.4 performing conversions and reading the data conversion fifo the cs5521/22/23/24/28 offers various modes of performing conversions. the sections that follow detail the differences between the conversion modes. the sections also provide examples illus- trating how to use the conversion modes with the channel-setup registers and to acquire conversions for further processing. while reading, note that the cs5521/22 have a fifo which is four words deep. the cs5523/24 have a fifo which is eight words deep and the cs5528 has a fifo which is sixteen
cs5521/22/23/24/28 ds317f2 35 conversion words deep. further note that the type of conversion(s) performed and the way to access the resulting data from the fifo is determined by the mc (multiple conversion), the lp (loop), the rc (read convert), and the dp (depth pointer) bits in the configuration register. 2.4.1 conversion protocol the cs552x offer six different conversion modes, which can be categorized into two main types of conversions: one-setup conversions, which refer- ence only one setup, and multiple-setup conver- sions, which reference any number of setups. the converter can be instructed to perform single con- versions or repeated conversions (with or without wait) in either of these modes, using the mc, lp, and rc bits in the configuration register. the mc bit controls whether the part will do one-setup or multiple-setup conversions. the lp bit controls whether the part will perform a single or repeated conversion set. when doing repeated conversion sets, the rc bit controls whether or not the convert- er will wait for the data from the current conversion set to be read before beginning the next conversion set. the sections that follow further detail the vari- ous conversion modes. 2.4.1.1 single, one-setup conversion (lp = 0 mc = 0 rc = x) in this conversion mode, the adc will perform a single conversion, referencing only one setup, and return to command mode after the data word has been fully read. the 8-bit command word contains the csrp bits, which instruct the converter which setup to use when performing the conversion. to perform a single, one-setup conversion, the mc and lp bits in the configuration register must be set to '0'. then, the 8-bit command word that refer- ences the desired setup must be sent to the convert- er. the adc will then perform a single conversion on the referenced setup, and sdo will fall to indi- cate that the conversion is complete. thirty-two sclks are then needed to read the conversion word from the data register. the first 8 sclks are used to clear the sdo flag. during the last 24 sclks, the data word will be output from the con- verter on the sdo line. the part returns to com- mand mode immediately after the data word has been read, where it waits for the next command to be issued. 2.4.1.2 repeated one-setup conversions with- out wait (lp = 1 mc = 0 rc = 0) in this conversion mode, the adc will repeatedly perform conversions, referencing only one setup. the 8-bit command word contains the csrp bits, which instruct the converter which setup to use when performing the conversion. note that in this mode, the part will continually perform conver- sions, and the user need not read every conversion as it becomes available. although conversions can be read whenever they are needed, they must be read within one conversion cycle (defined by the referenced setup), as the data word will be over- written when new conversion data becomes avail- able. the sdo line rises and falls to indicate the availability of new conversion data. when new data is available, the current conversion data will be lost, or in the case that the user has only read a part of the conversion word, the remainder of the conversion word will be corrupted. to perform repeated, one-setup conversions with no wait, the mc bit must be set to '0', the lp bit must be set to '1', and the rc bit must be set to '0' in the configuration register. then, the 8-bit com- mand word that references the desired setup must be sent to the converter. the adc will then begin performing conversions on the referenced setup, and sdo will fall to indicate when a conversion is complete, and data is available. thirty-two sclks are then needed to read the conversion word from the data register. the first 8 sclks are used to clear the sdo flag. during the last 24 sclks, the data word will be output from the converter on the
cs5521/22/23/24/28 36 ds317f2 sdo line. if, during the first 8 sclks, "00000000" is provided on sdi, the converter will remain in this conversion mode, and continue to perform conversions on the selected setup. to exit this conversion mode, "11111111" must be provid- ed on sdi during the first 8 sclks. if the user de- cides to exit, 24 more sclks are required to read the final conversion word from the data register and return to command mode. 2.4.1.3 repeated one-setup conversions with wait (lp = 1 mc = 0 rc = 1) in this conversion mode, the adc will repeatedly perform conversions, referencing only one setup. the 8-bit command word contains the csrp bits, which instruct the converter which setup to use when performing the conversion. note that in this mode, every conversion word must be read. the part will wait for the current conversion word to be read before performing the next conversion. to perform repeated, one-setup conversions with wait, the mc bit must be set to '0', the lp bit must be set to '1', and the rc bit must be set to '1' in the configuration register. then, the 8-bit command word that references the desired setup must be sent to the converter. the adc will then begin per- forming conversions on the referenced setup, and sdo will fall to indicate when a conversion is com- plete, and data is available. thirty-two sclks are then needed to read the conversion word from the data register. the first 8 sclks are used to clear the sdo flag. during the last 24 sclks, the data word will be output from the converter on the sdo line. if, during the first 8 sclks, "00000000" is provided on sdi, the converter will remain in this conversion mode, and continue to perform conver- sions on the selected setup after each data word is read. to exit this conversion mode, "11111111" must be provided on sdi during the first 8 sclks. if the user decides to exit, 24 more sclks are re- quired to read the final conversion word from the data register and return to command mode. 2.4.1.4 single, multiple-setup conversions (lp = 0 mc = 1 rc = x) in this conversion mode, the adc will perform sin- gle conversions, referencing multiple setups, and return to command mode after the data for all con- versions have been read. the csrp bits in the command word are ignored in this mode. instead, the depth pointer (dp3-dp0) bits in the configu- ration register are accessed to determine the num- ber of setups to reference when collecting the data. the number of setups referenced will be equal to (dp3-dp0) + 1, and will be accessed in order, be- ginning with setup1. to perform single, multiple-setup conversions, the mc bit must be set to '1', and the lp bit must be set to '0' in the configuration register. then, the 8-bit command word to start a conversion must be sent to the converter. because the csrp bits of the command word are ignored in this mode, a "start convert" command referencing any of the available setups will begin the conversions. the adc will then perform conversions using the appropriate number of setups (as dictated by the dp bits in the configuration register), beginning with setup1. the sdo line will fall after the final conversion to indicate that the data is ready. eight sclks, plus 24 sclks for each setup referenced are required to read the conversion words from the data fifo. the first 8 sclks are used to clear the sdo flag. ev- ery 24 bits thereafter consist of the data words of each setup that was referenced, until all of the data has been read from the part. the data word from setup1 is output first, followed by the data word from setup2, and so on for the appropriate number of setups. the part returns to command mode im- mediately after the final data word has been read, and waits for the next command to be issued.
cs5521/22/23/24/28 ds317f2 37 2.4.1.5 repeated multiple-setup conversions without wait (lp = 1 mc = 1 rc = 0) in this conversion mode, the adc will repeatedly perform conversions, referencing multiple setups. the csrp bits in the command word are ignored in this mode. instead, the depth pointer (dp3-dp0) bits in the configuration register are accessed to determine the number of setups to reference when collecting the data. the number of setups refer- enced will be equal to (dp3-dp0) + 1, and will be accessed in order, beginning with setup1. note that in this mode, the part will continually perform con- versions, looping back to setup1 when finished with each set, and the user need not read every con- version set as it becomes available. the sdo line rises and falls to indicate the availability of new conversion data sets. when new data is available, the current conversion data set will be lost, or in the case that the user has only read a part of the conver- sion set, the remainder of the conversion set will be corrupted. to perform repeated, multiple-setup conversions with no wait, the mc bit must be set to '1', the lp bit must be set to '1', and the rc bit must be set to '0' in the configuration register. then, the 8-bit command word to start a conversion must be sent to the converter. because the csrp bits of the command word are ignored in this mode, a "start convert" command referencing any of the available setups will begin the conversions. the adc will then perform conversions using the appropriate number of setups (as dictated by the dp bits in the configuration register), beginning with setup1. the sdo line will fall after the final conversion to indicate that the data is ready. eight sclks, plus 24 sclks for each setup referenced are required to read the conversion words from the data fifo. the first 8 sclks are used to clear the sdo flag. ev- ery 24 bits thereafter consist of the data words of each setup that was referenced, until all of the data has been read from the part. if, during the first 8 sclks, "00000000" is provided on sdi, the con- verter will remain in this conversion mode, and continue to perform conversions on the desired number of setups. to exit this conversion mode, "11111111" must be provided on sdi during the first 8 sclks. if the user decides to exit, 24 more sclks for each referenced setup are required to read the final conversion data set from the fifo and return to command mode. 2.4.1.6 repeated multiple-setup conversions with wait (lp = 1 mc = 1 rc = 1) in this conversion mode, the adc will repeatedly perform conversions, referencing multiple setups. the csrp bits in the command word are ignored in this mode. instead, the depth pointer (dp3-dp0) bits in the configuration register are accessed to determine the number of setups to reference when collecting the data. the number of setups refer- enced will be equal to (dp3-dp0) + 1, and will be accessed in order, beginning with setup1. note that in this mode, every conversion data set must be read. the part will wait for the current conversion data set to be read before performing the next set of conversions. to perform repeated, multiple-setup conversions with wait, the mc bit must be set to '1', the lp bit must be set to '1', and the rc bit must be set to '1' in the configuration register. then, the 8-bit com- mand word to start a conversion must be sent to the converter. because the csrp bits of the command word are ignored in this mode, a "start convert" command referencing any of the available setups will begin the conversions. the adc will then per- form conversions using the appropriate number of setups (as dictated by the dp bits in the configura- tion register), beginning with setup1. the sdo line will fall after the final conversion to indicate that the data is ready. eight sclks, plus 24
cs5521/22/23/24/28 38 ds317f2 sclks for each setup referenced are required to read the conversion words from the data fifo. the first 8 sclks are used to clear the sdo flag. ev- ery 24 bits thereafter consist of the data words of each setup that was referenced, until all of the data has been read from the part. if, during the first 8 sclks, "00000000" is provided on sdi, the con- verter will remain in this conversion mode, and be- gin performing the next set of conversions. to exit this conversion mode, "11111111" must be provid- ed on sdi during the first 8 sclks. if the user de- cides to exit, 24 more sclks for each referenced setup are required to read the final conversion data set from the fifo and return to command mode. 2.4.2 calibration protocol to perform a calibration, the user must send a com- mand byte with its msb=1, its pointer bits (csrp3-csrp0) set to address the desired setup to be calibrated, and the appropriate calibration bits (cc2-cc0) set to choose the type of calibration to be performed. proper calibration assumes that the csrs have been previously initialized because the information concerning the physical channel, its filter rate, gain range, and polarity, comes from the channel-setup register being addressed by the pointer bits in the command byte. once the csrs are initialized, all future calibra- tions can be performed with one command byte. once a calibration cycle is complete, sdo falls and the results are stored in either the gain or offset reg- ister for the physical channel being calibrated. note that if additional calibrations are performed on the same physical channel referenced by a different setup with different filter rates, gain ranges, or con- version modes, the last calibration results will re- place the effects from the previous calibration as only one offset and gain register is available per physical channel. one final note is that only one calibration is performed with each command byte. to calibrate all the channels additional calibration commands are necessary. 2.4.3 example of using the csrs to perform conversions and calibrations any time a calibration command is issued (cb=1 and proper cc2-cc0 bits set) or any time a normal conversion command is issued (cb=1, cc2=cc1=cc0=0, mc=0), the bits d6-d3 (or csrp3 - csrp0) in the command byte are used as pointers to address one of the setups in the chan- nel-setup registers (csrs). five example situations that a user might encounter when acquiring a con- version or calibrating the converter follow. these examples assume that the user is using a cs5528 (16 setups) and that its csrs are programmed with the following physical channel order: 6, 1, 6, 2, 6, 3, 6, 4, 6, 5, 6, 2, 6, 7, 6, 8. example 1: the configuration register has the following bits as shown: dp3-dp0 = xxxx, mc = 0, l = 0, rc = x. the command issued is 11110000. these settings instruct the converter to convert the 15th setup once, as cpb3 - cpb0 = 1110 (which happens to be physical channel 6 in this example). sdo falls after physical channel 6 is converted. to read the conversion results, 32 sclks are then re- quired. once acquired, the serial port returns to the command mode. example 2: the configuration register has the following bits as shown: dp3-dp0 = xxxx, mc = 0, lp = 1, rc = 1. the command byte issued is 10011000. these settings instruct the converter to repeatedly convert the fourth setup as cpb3-cpb0 = 0011 (which happens to be physical channel 2 in this ex- ample). sdo falls after physical channel 2 is con- verted. to read the conversion results 32 sclks are required. the first 8 sclks are needed to clear the sd0 flag. if 00000000 is provided to the sdi pin during the first 8 sclks, the conversion is per- formed again on physical channel 2. the converter will remain in data mode until 11111111 is pro- vided during the first 8 sclks following the fall of
cs5521/22/23/24/28 ds317f2 39 sd0. after 11111111 is provided, 24 additional sclks are required to transfer the last 3 bytes of conversion data before the serial port will return to the command mode. example 3: the configuration register has the following bits as shown: dp3-dp = 0101, mc = 1, lp = 0, rc = x. the command issued is 1xxxx000. these settings instruct the converter to perform a single conversion on six setups once. the order in which the channels are converted is 6, 1, 6, 2, 6, and 3. sdo falls after physical channel 3 is converted. to read the 6 conversion results 8 sclks are re- quired to clear the sd0 flag. then 144 additional sclks are required to read the conversion data from the fifo. again, the order in which the data is provided is the same as the order in which the channels are converted. after the last 3 bytes of the conversion data corresponding to physical channel 3 is read, the serial port automatically returns to the command mode where it will remain until the next valid command byte is received. example 4: the configuration register has the following bits as shown: dp3-dp0 = 1001, mc = 1, lp = 1, rc = 0. the command byte issued is 1xxxx000. these settings instruct the converter to repeatedly perform multiple-setup conversions using ten setups. the order in which the channels are converted is: 6, 1, 6, 2, 6, 3, 6, 4, 6, 5. sdo falls after physical channel 5 is converted. to read the 10 conversion results 8 sclks with sdi = 0 are re- quired to clear the sd0 flag. then 240 more sclks are required to read the conversion data from the fifo. the order in which the data is pro- vided is the same as the order in which the channels are converted. the first 3 bytes of data correspond to the first setup which in this example is physical channel 6; the next 3 bytes of data correspond to the second setup which in this example is physical channel 1; and, the last 3 bytes of data corresponds to 10th setup which here is physical channel 5. since the setups are converted in the background, while the data is being read, the user must finish reading the conversion data fifo before it is updat- ed with new conversions. to exit this conversion mode the user must provide 11111111 to sdi during the first 8 sclks. if a byte of 1s is provid- ed, the serial port returns to the command mode only after the conversion data fifo is emptied (in this case 10 conversions are performed). note that in this example physical channel 6 is converted five times. each conversion could be with the same or different filter rates depending on the setting of set- ups 1, 3, 5, 7 and 9. note that there is only one off- set and one gain register per physical channel. therefore, any physical channel can only be cali- brated for the gain range selected during calibra- tion. specifying a different gain range in the setup other than the range that was calibrated will result in a gain error. example 5: the configuration register has the following bits as shown: dp3-dp0 = xxxx, mc = x, lp = x, rc = x. the command issued is 10101101. these settings instruct the converter to perform a system offset calibration of the 6th setup (which is physical channel 3 in this example). during cali- bration, the serial port remains in the command mode. once the calibration is completed, sdo falls. to perform additional calibrations, more commands have to be issued. notes: 1)the configuration register must be written before channel-setup registers (csrs) because the depth information contained in the configuration regis- ter defines how many of the csrs to use. 2) the csrs need to be written irrespective of single conversion or multiple single conversion mode. 3) when single-setup conversions (mc = 0) are de- sired, the channel address is embedded in the command byte. in the multiple-setup conversion mode (mc = 1), channels are selected in a pre- programmed order based on information con- tained in the csrs and the depth bits (dp3-dp0)
cs5521/22/23/24/28 40 ds317f2 of the configuration register. 4) once the csrs are programmed, repeated conver- sions on up to 16 setups can be performed by is- suing only one command byte. 5) the single conversion mode also requires only one command, but whenever another or a different single conversion is wanted, this command or a modified version of it has to be issued again. 6) the null command is used to keep the serial port in command mode, once it is in command mode. 2.5 conversion output coding the cs5521/22/23/24/28 devices output 16-bit (cs5521/23) and 24-bit (cs5522/24/28) data con- version words. to read a conversion word, the user must read the conversion data fifo. the conver- sion data fifo is up to 192 bits long and outputs the conversions msb first. the last byte of the con- version data word (cs5521/23 only) contains data monitoring flags. the channel indicator (ci) bits keep track of which physical channel was convert- ed, and the overrange flag (of) and the oscillation detect (od) bits monitor conversions to determine if a valid conversion was performed. refer to the conversion data fifo descriptions section for more details. the cs5521/22/23/24/28 output data conversions in binary format when operating in unipolar mode and in two's complement when operating in bipolar mode. refer to the conversion data fifo de- scriptions section for more details. note: vfs in the table equals the voltage between ground and full scale for any of the unipolar gain ranges, or the voltage between full scale for any of the bipolar gain ranges. see text about error flags under overrange conditions. unipolar input voltage offset binary bipolar input voltage two's complement unipolar input voltage offset binary bipolar input voltage two's complement >(vfs-1.5 lsb) ffff >(vfs-1.5 lsb) 7fff >(vfs-1.5 lsb) ffffff >(vfs-1.5 lsb) 7fffff vfs-1.5 lsb ffff ------ fffe vfs-1.5 lsb 7fff ------ 7ffe vfs-1.5 lsb ffffff ------ fffffe vfs-1.5 lsb 7fffff ------ 7ffffe vfs/2-0.5 lsb 8000 ------ 7fff -0.5 lsb 0000 ------ ffff vfs/2-0.5 lsb 800000 ------ 7fffff -0.5 lsb 000000 ------ ffffff +0.5 lsb 0001 ------ 0000 -vfs+0.5 lsb 8001 ------ 8000 +0.5 lsb 000001 ------ 000000 -vfs+0.5 lsb 800001 ------ 800000 <(+0.5 lsb) 0000 <(-vfs+0.5 lsb) 8000 <(+0.5 lsb) 000000 <(-vfs+0.5 lsb) 800000 table 6. output coding for 16-bit cs5521/23 and 24-bit cs5522/24/28 cs5521/23 16-bit output coding cs5522/24/28 24-bit output coding
cs5521/22/23/24/28 ds317f2 41 2.5.1 conversion data fifo descriptions cs5521/23 (each 16-bit conversions) cs5522/24/28 (each 24-bit conversion levels) conversion data bits [23:8 for cs5521/23; 23:0 for cs5522/24/28] these bits depict the latest output conversion. od (oscillation detect flag bit) 0 bit is clear when oscillatory condition in modulator does not exist (bit is read only). 1 bit is set any time an oscillatory condition is detected in the modulator. this does not occur under normal operation conditions, but may occur when the input is extremely overranged. the od flag will be cleared to logic 0 when the modulator becomes stable. of (over-range flag bit) 0 bit is clear when over-range condition has not occurred (bit is read only). 1 bit is set when input signal is more positive than the positive full scale, more negative than zero (unipolar mode) or when the input is more negative than the negative full scale (bipolar mode). ci (channel indicator bits) [1:0] these bits indicate which physical input channel was converted. 00 physical channel 1 (cs5521/23 only) 01 physical channel 2 (cs5521/23 only) 10 physical channel 3 (cs5523 only) 11 physical channel 4 (cs5523 only) d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 msb14131211109 87654 d11 d10d9d8d7d6 d5 d4d3d2d1d0 321lsb1110ci1ci0odof d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 msb 2221201918 17 1615141312 d11 d10d9d8d7d6 d5 d4d3d2d1d0 11 109876 5 4321lsb
cs5521/22/23/24/28 42 ds317f2 2.6 digital filter the cs5521/22/23/24/28 have eight different lin- ear phase digital filters which set the output word rates (owrs) shown in table 3. these rates as- sume that xin is 32.768 khz. each of the filters has a magnitude response similar to that shown in figure 18. the filters are optimized to settle to full accuracy every conversion and yield better than 80 db rejection for both 50 and 60 hz with output word rates at or below 15.0 hz. the converters digital filters scale with xin. for example with an output word rate of 15 hz, the fil- ters corner frequency is typically 12.7 hz using a 32.768 khz clock. if xin is increased to 65.536 khz the owr doubles and the filters cor- ner frequency moves to 25.4 hz. 2.7 clock generator the cs5521/22/23/24/28 include a gate which can be connected with an external crystal to provide the master clock for the chip. the chips are designed to operate using a low-cost 32.768 khz tuning fork type crystal. one lead of the crystal should be con- nected to xin and the other to xout. lead lengths should be minimized to reduce stray capacitance. note that the oscillator circuit will also operate with a 100 khz tuning fork type crystal. the converters will operate with an external (cmos compatible) clock with frequencies up to 130 khz (cs5521/23) or 200 khz (cs5522/24/28). figures 19 and 20 detail the cs5521/23 and cs5522/24/28s performance (respectively) at in- creased clock rates. the 32.768 khz crystal is normally specified as a time-keeping crystal with tight specifications for both initial frequency and for drift over tempera- ture. to maintain excellent frequency stability, these crystals are specified only over limited oper- ating temperature ranges (i.e. -10 c to +60 c). however, applications with the cs5521/22/23/24/28 dont generally require such tight tolerances. figure 18. filter response (normalized to output word rate = 1) 0.0004 0.0006 0.0008 0.001 0.0012 0.0014 0.0016 0.0018 0.002 30 50 70 90 110 130 xin (khz) linearity error (%fs) figure 19. typical linearity error for cs5521/23 0.0004 0.0005 0.0006 0.0007 0.0008 0.0009 0.001 0.0011 0.0012 0.0013 20 40 60 80 100 120 140 160 180 200 xin (khz) linearity error (%fs) figure 20. typical linearity error for cs5522/24/28
cs5521/22/23/24/28 ds317f2 43 2.8 power supply arrangements the cs5521/22/23/24/28 a/d converters are de- signed to operate from a single +5 v analog supply and a single +5 v or +3 v digital supply. a -2.1 v supply is usually generated from the charge pump drive to provide power to the instrumentation am- plifiers nbv (negative bias voltage) pin. figure 21 illustrates the cs5522 connected with a +5 v analog supply and with the external compo- nents required for the charge pump drive. this en- ables the cs5522 to measure ground referenced signals with magnitudes down to 100 mv. figure 22 illustrates the cs5522 connected to mea- sure ground referenced unipolar signals of a posi- tive polarity using the 1 v, 2.5 v, and 5 v ranges on the converter. for the 25 mv, 55 mv, and 100 mv ranges, the signals being digitized must have a common mode between +1.85 to +2.65 v (nbv = 0 v). although cs5521/22/23/24/28 are optimized for the measurement of thermocouple outputs, they are also well suited for the measurement of ratiometric bridge transducer outputs. figure 23 illustrates the cs5522 connected to measure the output of a rati- ometric differential bridge transducer while operat- ing from a single +5 v supply. bridge outputs may range from 5 mv to 400 mv. see the digital gain scaling section about manipulating the gain regis- ter to achieve optimum gain scaling. xout vd+ va+ vref+ vref- dgnd nbv ain1+ sclk sdo sdi cs5522 xin cpd cs 10 w +5v analog supply 0.1 m f0.1 m f 20 19 3 1 agnd 214 11 10 15 12 8 9 13 5 optional clock source serial data interface 7 32.768 ~ 100 khz 2.5v up to 100 mv input ain1- 4 10 k w 0.1 m f 10 m f 1n4148 1n4148 + bav199 18 ain2+ 17 ain2- 16 a1 6 a0 charge-pump network for vd+ = 5v only and xin = 32.768 khz. logic outputs: a0 - a1 switch from va+ to agnd. 10 k w 301 w 499 w +5v v+ r lm334 absolute current reference v- cold junction bat85 0.033 m f figure 21. cs5522 configured to use on-chip charge pump to supply nbv
cs5521/22/23/24/28 44 ds317f2 xout vd+ va+ vref+ vref- dgnd nbv ain1+ ain1- sclk sdo sdi cs5522 xin cpd cs 10 w +5v analog supply 0.1 m f 0.1 m f 20 19 3 4 1 agnd 214 11 10 15 12 8 9 13 5 optional clock source serial data interface 7 32.768 ~ 100 khz 0 to +5v input 18 ain2+ 17 ain2- 16 a1 6 a0 + - cm = 0 to va+ figure 22. cs5522 configured for ground-referenced unipolar signals xout vd+ va+ vref+ vref- dgnd nbv ain1+ ain1- sclk sdo sdi cs5522 xin cpd cs 10 w +5v analog supply 0.1 m f 0.1 m f + - 20 19 3 4 1 agnd 2 14 11 10 15 12 8 9 13 5 optional clock source serial data interface 7 32.768 ~ 100khz 18 ain2+ 17 ain2- 16 a1 6 a0 figure 23. cs5522 configured for single supply bridge measurement
cs5521/22/23/24/28 ds317f2 45 2.8.1 charge pump drive circuits the cpd (charge pump drive) pin of the converter can be used with external components (shown in figure 21) to develop an appropriate negative bias voltage for the nbv pin. when cpd is used to gen- erate the nbv, the nbv voltage is regulated with an internal regulator loop referenced to va+. therefore, any change on va+ results in a propor- tional change on nbv. with va+ = 5 v, nbvs regulation is set proportional to va+ at approxi- mately -2.1 v. figure 24 illustrates a charge pump circuit when the converters are powered from a +3.0 v digital supply. alternatively, the negative bias supply can be generated from a negative supply voltage or a resistive divider as illustrated in figure 25. for ground based signals with the instrumentation amplifier engaged (when in the 25 mv, 55 mv, or 100 mv ranges), the voltage on the nbv pin should at no time be less negative than -1.8 v or more negative than -2.5 v. to prevent excessive voltage stress to the chip when the instrumentation amplifier isnt engaged (when in the 1 v, 2.5 v, or 5 v ranges) the nbv voltage should not be more negative than -2.5 v. the components in figure 21 are the preferred components for the cpd filter. however, smaller capacitors can be used with acceptable results. the 10 m f ensures very low ripple on nbv. intrinsic safety requirements prohibit the use of electrolytic capacitors. in this case, four 0.47 m f ceramic ca- pacitors in parallel can be used. note: the charge pump is designed to nominally provide 400 m a of current for the instrumentation amplifier when a 0.033 m f pumping capacitor is used (xin = 32.768 khz). when a larger pumping capaci- tor is used, the charge pump can source more current to power external loads. refer to applications note 152 using the cs5521/23, cs5522/24/28, and cs5525/26 charge pump drive for external loads for more details on using the charge pump with exter- nal loads. 2.9 digital gain scaling the cs5521/22/23/24 and cs5528 all feature a gain register capable of being scaled from 0.6 to 4- 2 -22 in decimal. the specified ranges of the con- verter are defined with a voltage reference of 2.5 v and the gain register set at approximately 1.0. the gain register can be manipulated to scale the input for ranges other than those specified. for example, when using a 2.5 v voltage reference, and the 25 mv input range setting, the gain register can be changed from 1.000 to 2.000 (shift the entire regis- ter contents to the left one position) to achieve an input span of 12.5 mv. under this condition the full span of the converter codes will appear across a 12.5 mv span. the amount of noise in the con- figure 24. charge pump drive circuit for vd+ = 3 v -5v nbv 30.1k w 34.8k w 2n5087 or similar -5v 2.1k w 2.0k w nbv + 10 m f 10 m f + bat85 bat85 figure 25. alternate nbv circuits
cs5521/22/23/24/28 46 ds317f2 verter stays constant but the number of codes af- fected is doubled because the code size has been reduced by half. the converter input ranges are specified with a voltage reference of 2.5 v. the device can be op- erated with the reference tied directly to the +5 v supply. when this is done, the input span of the in- put ranges is doubled; the 25 mv range actually be- comes a 50 mv range. the gain register can be set to 2.0 (shift contents left one bit) and the input range will be scaled back to 25 mv. since the gain register can actually be as great as 4-2 -22 decimal, one could scale the input span on the 25 mv range to accept an analog full scale span of about 6.25 mv. this is useful for ratiometric bridge mea- surement of low level differential outputs. the gain register can also be scaled manually to a value lower than 1.0. it is not recommended to use the devices with the gain register scaled lower than 0.6. this can enable the converter to accept a 40 mv input signal on the 25 mv range when using a voltage reference of 2.5 v. caution though in scaling the gain register below 1.0 on the 100 mv, 2.5 and 5 volt ranges as the analog signal path into the converter may saturate before the expected full scale code output is produced by the converter. note that digital gain scaling will directly influence the number of digital output codes affected by noise. the effects can be analytically determined by calculating the size of the codes (v/count) which result from a given gain scaling condition and relating the amount of noise in the converter relative to the determined code size. the evalua- tion board for the converter is a useful tool to aid the assessment of noise performance with various voltage reference values, input range settings, and gain register settings. the evaluation board sup- ports noise analysis through data capture and noise histogram analysis. 2.10 getting started the cs5521/22/23/24/28 have many features. from a software programmers perspective, what should be done first? to begin, a 32.768 khz crys- tal takes approximately 500 ms to start-up. to ac- commodate for this, it is recommended that a software delay of approximately 500 ms to 1 sec- ond precede the processors adc initialization code before any registers are accessed in the adc. this delay time is dependent on the start-up delay of the clock source. if a cmos clock source with no start-up delay is being used to drive the adc, then this delay is not necessary. the converters include an on-chip power on reset circuit to automatically reset the adcs shortly af- ter power up. when power to the cs5521/22/23/24/28 is applied, the chips are held in a reset condition until the 32.768 khz oscillator has started and a counter-timer elapses. the counter-timer counts 2006 oscillator clock cycles to make sure the oscillator is fully stable. during this time-out period the serial port logic is reset and the rv (reset valid) bit in the configuration regis- ter is set to indicate that a valid reset occurred. in normal start-up conditions, this power-on-reset cir- cuit should reset the chip when power is applied. if your application may experience abnormal power start-up conditions, the following sequence of in- structions should be performed to guarantee the converter begins proper operation: 1) after power is applied, initialize the serial port using the serial port synchronization sequence. 2) write a 1 to the reset bit (rs) of the configu- ration register to reset the converter. 3) read the configuration register to determine if the reset valid bit (rv) is set to 1. if the rv bit is not set, the configuration register should be read again. 4) when the rv bit has been set to 1, reset the rs bit back to 0 by writing to 0x000000 to the
cs5521/22/23/24/28 ds317f2 47 configuration register. note that while the rs bit is set to 1 all other register bits in the adc will be reset to their default state, and the rs bit must be set to 0 for normal operation of the converters. once the rs bit has been set to 0, the adc is placed in the command state were it waits for a val- id command to execute. the next step is to load the configuration register and then the channel setup registers with conditions that you have decided. if you need to do a factory calibration, perform offset and gain calibrations for each channel that is to be used. then off-load the offset and gain register contents into eeprom. these registers can then be initialized to these conditions when the instru- ment is used in normal operation. once calibration is ready, input the command to start conversions in the mode you have selected via the configuration register bits. monitor the sdo pin for a flag that the data is ready and read conversion data. 2.11 pcb layout the cs5521/22/23/24/28 should be placed entirely over an analog ground plane with both the agnd and dgnd pins of the device connected to the an- alog plane. place the analog-digital plane split im- mediately adjacent to the digital portion of the chip. if separate digital (vd+) and analog (va+) sup- plies are used, it is recommended that a diode be placed between them (the cathode of the diode should point to va+). if the digital supply comes up before the analog supply, the adc may not start up properly. note: see the cdb5521/22/23/24/28 data sheet for suggest- ed layout details and applications note 18 for more detailed layout guidelines. before layout, please call for our free schematic review service.
cs5521/22/23/24/28 48 ds317f2 3. pin descriptions 5 6 7 813 14 15 16 17 18 19 20 vref+ vref- ain2+ ain2- a1 sclk vd+ dgnd sdi cpd a0 nbv ain1- ain1+ va+ agnd 9 10 11 12 sdo xout xin cs serial data input charge pump drive logic output negative bias voltage differential analog input differential analog input positive analog power analog ground crystal in chip select voltage reference input voltage reference input differential analog input differential analog input logic output serial clock input positive digital power digital ground serial data out crystal out 1 2 3 4 cs5521 cs5522 1 2 3 4 5 6 7 817 18 19 20 21 22 23 24 vref+ vref- ain2+ ain2- ain4+ ain4- a1 sclk a0 nbv ain3- ain3+ ain1- ain1+ va+ agnd 9 10 11 12 13 14 15 16 vd+ dgnd sdo xout xin cs sdi cpd logic output negative bias voltage differential analog input differential analog input differential analog input differential analog input positive analog power analog ground crystal in chip select serial data input charge pump drive voltage reference input voltage reference input differential analog input differential analog input differential analog input differential analog input logic output serial clock input positive digital power digital ground serial data out crystal out cs5524 cs5523 1 2 3 4 5 6 7 817 18 19 20 21 22 23 24 vref+ vref- ain3+ ain4+ ain7+ ain8+ a1 sclk a0 nbv ain6+ ain5+ ain2+ ain1+ va+ agnd 9 10 11 12 13 14 15 16 vd+ dgnd sdo xout xin cs sdi cpd voltage reference input voltage reference input logic output serial clock input positive digital power digital ground serial data out crystal out logic output negative bias voltage single-ended analog input single-ended analog input single-ended analog input single-ended analog input positive analog power analog ground crystal in chip select serial data input charge pump drive cs5528 single-ended analog input single-ended analog input single-ended analog input single-ended analog input
cs5521/22/23/24/28 ds317f2 49 3.1 clock generator xin; xout - crystal in; crystal out. a gate inside the chip is connected to these pins and can be used with a crystal to provide the master clock for the device. alternatively, an external (cmos compatible) clock can be supplied into the xin pin to provide the master clock for the device. 3.2 control pins and serial data i/o cs - chip select. when active low, the port will recognize sclk. when high the sdo pin will output a high impedance state. cs should be changed when sclk = 0. sdi - serial data input. sdi is the input pin of the serial input port. data will be input at a rate determined by sclk. sdo - serial data output. sdo is the serial data output. it will output a high impedance state if cs =1. sclk - serial clock input. a clock signal on this pin determines the input/output rate of the data for the sdi/sdo pins respectively. this input is a schmitt trigger to allow for slow rise time signals. the sclk pin will recognize clocks only when cs is low. a0, a1 - logic outputs. the logic states of a0-a1 mimic the states of the d22/d10-d23/d11 bits of the channel-setup register. logic output 0 = agnd, and logic output 1 = va+. 3.3 measurement and reference inputs ain1+, ain1-, ain2+, ain2- ain3+, ain3-, ain4+, ain4- - differential analog input. differential input pins into the cs5522 and cs5524 devices. ain1+, ain2+, ain3+, ain4+, ain5+, ain6+, ain7+, ain8+ - single-ended analog input. single-ended input pins into the cs5528. vref+, vref- - voltage reference input. fully differential inputs which establish the voltage reference for the on-chip modulator.
cs5521/22/23/24/28 50 ds317f2 nbv - negative bias voltage. input pin to supply the negative supply voltage for the 20x gain instrumentation amplifier and coarse/fine charge buffers. may be tied to agnd if ain+ and ain- inputs are centered around +2.5 v; or it may be tied to a negative supply voltage (-2.1 v typical) to allow the amplifier to handle low level signals more negative than ground. when using the cs5528 in either the 25 mv, 55 mv or 100 mv range, the analog inputs are expected to be ground referenced; therefore, nbv must be between -1.8 to -2.5 to ensure proper operation. cpd - charge pump drive. square wave output used to provide energy for the charge pump. 3.4 power supply connections va+ - positive analog power. positive analog supply voltage. nominally +5 v. vd+ - positive digital power. positive digital supply voltage. nominally +3.0 v or +5 v. agnd - analog ground. analog ground. dgnd - digital ground. digital ground.
cs5521/22/23/24/28 ds317f2 51 4. specification definitions linearity error the deviation of a code from a straight line which connects the two endpoints of the a/d converter transfer function. one endpoint is located 1/2 lsb below the first code transition and the other endpoint is located 1/2 lsb beyond the code transition to all ones. units in percent of full-scale. differential nonlinearity the deviation of a code's width from the ideal width. units in lsbs. full scale error the deviation of the last code transition from the ideal [{(vref+) - (vref-)} - 3/2 lsb]. units are in lsbs. unipolar offset the deviation of the first code transition from the ideal (1/2 lsb above the voltage on the ain- pin.). when in unipolar mode (u/b bit = 1). units are in lsbs. bipolar offset the deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 lsb below the voltage on the ain- pin). when in bipolar mode (u/b bit = 0). units are in lsbs. 5. ordering guide model number bits channels linearity error (max) temperature range package cs5521-ap 16 2 0.003% -40 c to +85 c 20-pin 0.3" plastic dip cs5521-as 16 2 0.003% -40 c to +85 c 20-pin 0.2" plastic ssop cs5522-ap 24 2 0.0015% -40 c to +85 c 20-pin 0.3" plastic dip cs5522-as 24 2 0.0015% -40 c to +85 c 20-pin 0.2" plastic ssop cs5523-ap 16 4 0.003% -40 c to +85 c 24-pin 0.3" plastic dip cs5523-as 16 4 0.003% -40 c to +85 c 24-pin 0.2" plastic ssop cs5524-ap 24 4 0.0015% -40 c to +85 c 24-pin 0.3" plastic dip cs5524-as 24 4 0.0015% -40 c to +85 c 24-pin 0.2" plastic ssop cs5528-ap 24 8 0.0015% -40 c to +85 c 24-pin 0.3" plastic dip cs5528-as 24 8 0.0015% -40 c to +85 c 24-pin 0.2" plastic ssop
cs5521/22/23/24/28 52 ds317f2 6. package dimension drawings notes: 1. positional tolerance of leads shall be within 0.25 mm (0.010 in.) at maximum material condition, in relation to seating plane and each other. 2. dimension ea to center of leads when formed parallel. 3. dimension e does not include mold flash. inches millimeters dim min nom max min nom max a 0.000 -- 0.210 0.00 -- 5.33 a1 0.015 0.020 0.025 0.38 0.508 0.64 a2 0.115 0.130 0.195 2.92 3.302 4.95 b 0.014 0.018 0.022 0.36 0.4572 0.56 b1 0.045 0.058 0.070 1.14 1.46 1.78 c 0.008 0.010 0.014 0.20 0.25 0.36 d 0.980 1.030 1.060 24.89 26.162 26.92 e 0.300 0.310 0.325 7.62 7.874 8.26 e1 0.240 0.252 0.280 6.10 6.40 7.11 e 0.090 0.100 0.110 2.29 2.54 2.79 ea 0.280 0.30 0.320 7.11 7.62 8.13 eb 0.300 0.37 0.430 7.62 9.40 10.92 ec 0.000 -- 0.060 0.00 -- 1.52 l 0.115 0.130 0.150 2.92 3.302 3.81 0 8 15 0 8 15 jedec # : ms-001 controling dimension is inches 20 pin plastic (pdip) (300 mil) package drawing e1 d seating plane b1 e b a l a1 top view bottom view side view 1 ea c a2 e ec eb
cs5521/22/23/24/28 ds317f2 53 inches millimeters dim min nom max min nom max a 0.000 -- 0.210 0.00 -- 5.33 a1 0.015 0.020 0.025 0.38 0.51 0.64 a2 0.115 0.130 0.195 2.92 3.30 4.95 b 0.014 0.018 0.022 0.36 0.46 0.56 b1 0.045 0.058 0.070 1.14 1.46 1.78 c 0.008 0.010 0.014 0.20 0.25 0.36 d 1.230 1.255 1.280 31.24 31.88 32.51 e 0.300 0.310 0.325 7.62 7.87 8.26 e1 0.240 0.252 0.280 6.10 6.40 7.11 e 0.090 0.100 0.110 2.29 2.54 2.79 ea 0.280 0.30 0.320 7.11 7.62 8.13 eb 0.300 0.37 0.430 7.62 9.40 10.92 ec 0.000 -- 0.060 0.00 -- 1.52 l 0.115 0.130 0.150 2.92 3.30 3.81 0 8 15 0 8 15 jedec # : ms-001 controling dimension is inches 24 pin skinny plastic (pdip) (300 mil) package drawing e1 d seating plane b1 e b a l a1 top view bottom view side view 1 ea c a2 e ec eb
cs5521/22/23/24/28 54 ds317f2 notes: 1. d and e1 are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension b does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of b dimension at maximum material condition. dambar intrusion shall not reduce dimension b by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a -- -- 0.084 -- -- 2.13 a1 0.002 0.006 0.010 0.05 0.13 0.25 a2 0.064 0.068 0.074 1.62 1.73 1.88 b 0.009 -- 0.015 0.22 -- 0.38 2,3 d 0.272 0.2834 0.295 6.90 7.20 7.50 1 e 0.291 0.307 0.323 7.40 7.80 8.20 e1 0.197 0.209 0.220 5.00 5.30 5.60 1 e 0.022 0.026 0.030 0.55 0.65 0.75 l 0.025 0.03 0.041 0.63 0.75 1.03 0 4 8 0 4 8 jedec #: mo-150 controling dimension is millimeters. 20l ssop package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
cs5521/22/23/24/28 ds317f2 55 notes: 1. d and e1 are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension b does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of b dimension at maximum material condition. dambar intrusion shall not reduce dimension b by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a -- -- 0.084 -- -- 2.13 a1 0.002 0.006 0.010 0.05 0.13 0.25 a2 0.064 0.068 0.074 1.62 1.73 1.88 b 0.009 -- 0.015 0.22 -- 0.38 2,3 d 0.311 0.323 0.335 7.90 8.20 8.50 1 e 0.291 0.307 0.323 7.40 7.80 8.20 e1 0.197 0.209 0.220 5.00 5.30 5.60 1 e 0.022 0.026 0.030 0.55 0.65 0.75 l 0.025 0.03 0.041 0.63 0.75 1.03 0 4 8 0 4 8 jedec #: mo-150 controling dimension is millimeters. 24l ssop package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view

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